Datasheet
Controller
(FPGA)
+
-
+
-
Ch. 1
UV1
OV6
OV5
OV4
OV3
OV2
V+ = 3.3V
OV1
+IN1
-IN1
GND
AO
CO1
*
*
COPOL
UV6
UV5
UV4
UV3
UV2
UV1
* Open
Drain
AOSEL
*
OV1
RESERVED
Ch. 6
+IN6
-IN6
CO6
REF
REF
LMV7231
COPOL
REF
UV6 OV6
REF
SW
L1
C2
R2
R3
BST
VCC
C4
C5
D1
RON/SD
VIN
R1
Input = 9V-42V
C1
1.0 PF
115k
3k
3k
100 PH
0.1
PF
22 PF
0.01PF
V
OUT
= 5V
C3
0.1 PF
C6
C7
R6
0.01 PF
121k
2200
pF
LM25007
RTN
R7
R8
R9
1.15k
10
95.3
R10
10k
R12
10k
ON/OFF
C8
0.1 PF
C9
*optional
RCL
R5
200k
FB
R11
10k
V+
V+
V+
LMV7231
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SNOSB45E –FEBRUARY 2010–REVISED MARCH 2013
Resistor R6 and capacitors C6, C7 are utilized to minimize output ripple voltage per the LM25007 evaluation
board application note.
The comparator voltage window is set to 5V +/- 5% by R7=1.15kΩ , R8=10Ω, R9=95.3Ω. See 3 RESISTOR
VOLTAGE DIVIDER SELECTION section in the Application Information section of the datasheet for details on
how to set the comparator voltage window.
With components selected the output ripple voltage seen on the LM25007 is approximately 30 - 35mV and is
reduced to about 4mV at the comparator input, +IN1, by the resistor divider. This ripple voltage can be reduced
multiple ways. First, user can operate the device in continuous conduction mode rather than discontinuous
conduction mode. To do this increase the load current of the device (see LM25007 datasheet for more details).
However, make sure not to exceed the power rating of the resistors in the resistor ladder. Second, ripple can be
reduced further with a bypass cap, C9, at the resistor divider. If desired a user can select a 1uF capacitor to
achieve less than 3mV ripple at +IN1. However, there is a tradeoff and adding capacitance at this node will lower
the system response time.
Figure 40. Power Supply Supervision
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