Datasheet

LMV7219
SNOS458F –APRIL 2000–REVISED MARCH 2013 www.ti.com
3) Calculate R1, where R1 = R3 X(V
HB
/V
CC
)
4) Choose the trip point for V
IN
rising. This is the threshold voltage (V
THR
) at which the comparator switches from
low to high as V
IN
rises about the trip point.
5) Calculate R2 as follows:
(3)
6) Verify the trip voltage and hysteresis as follows:
(4)
This method is recommended for additional hysteresis of up to a few hundred millivolts. Beyond that, the
impedance of R3 is low enough to affect the bias string and adjustment of R1 may be also required.
Figure 18. Additional Hysteresis
Circuit Layout and Bypassing
The LMV7219 requires high-speed layout. Follow these layout guidelines:
1. Power supply bypassing is critical, and will improve stability and transient response. A decoupling capacitor
such as 0.1µF ceramic should be placed as close as possible to V
+
pin. An additional 2.2µF tantalum
capacitor may be required for extra noise reduction.
2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize unwanted parasitic
feedback around the comparator.
3. The device should be soldered directly to the PC board instead of using a socket.
4. Use a PC board with a good, unbroken low inductance ground plane. Make sure ground paths are low-
impedance, especially were heavier currents are flowing.
5. Input traces should be kept away from output traces. This can be achieved by running a topside ground
plane between the output and inputs.
6. Run the ground trace under the device up to the bypass capacitor to shield the inputs from the outputs.
7. To prevent parasitic feedback when input signals are slow-moving, a small capacitor of 1000pF or less can
be placed between the inputs. It can also help eliminate oscillations in the transition region. However, this
capacitor can cause some degradation to tpd when the source impedance is low.
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