Datasheet

LMV712-N
www.ti.com SNOS534G –MAY 2004–REVISED MARCH 2010
The circuit in Figure 35 is an improvement to the one in Figure 34 because it provides DC accuracy as well as
AC stability. In this circuit, R
F
provides the DC accuracy by using feed-forward techniques to connect V
IN
to R
L
.
C
F
and R
ISO
serve to counteract the loss of phase margin by feeding the high frequency component of the output
signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop.
Increased capacitive drive is possible by increasing the value of C
F
. This in turn will slow down the pulse
response.
Figure 35.
LATCHUP
CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR (silicon controlled rectifier)
effects. The input and output pins look similar to the gate of the SCR. There is a minimum current required to
trigger the SCR gate lead. The LMV712-N is designed to withstand 150mA surge current on all the pins. Some
resistive method should be used to isolate any capacitance from supplying excess current to the pins. In addition,
like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will
also inhibit latchup susceptibility.
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