Datasheet

LMV710-N, LMV711-N, LMV715-N
SNOS519J –APRIL 2000–REVISED MARCH 2013 www.ti.com
APPLICATION INFORMATION
Supply Bypassing
The application circuits in this datasheet do not show the power supply connections and the associated bypass
capacitors for simplification. When the circuits are built, it is always required to have bypass capacitors. Ceramic
disc capacitors (0.1 µF) or solid tantalum (1 µF) with short leads, and located close to the IC are usually
necessary to prevent interstage coupling through the power supply internal impedance. Inadequate bypassing
will manifest itself by a low frequency oscillation or by high frequency instabilities. Sometimes, a 10 µF (or larger)
capacitor is used to absorb low frequency variations and a smaller 0.1 µF disc is paralleled across it to prevent
any high frequency feedback through the power supply lines.
Shutdown Mode
The LMV711/LMV715 have a shutdown pin. To conserve battery life in portable applications, they can be
disabled when the shutdown pin voltage is pulled low. For LMV711 during shutdown mode, the output stays at
about 50 mV from the lower rail, and the current drawn from the power supply is 0.2 µA (typical). This makes the
LMV711 an ideal solution for power sensitive applications. For the LMV715 during shutdown mode, the output
will be “Tri-stated”.
The shutdown pin should never be left unconnected. In applications where shutdown operation is not needed
and the LMV711 or LMV715 is used, the shutdown pin should be connected to V
+
. Leaving the shutdown pin
floating will result in an undefined operation mode and the device may oscillate between shutdown and active
modes.
Rail-to-Rail Input
The rail-to-rail input is achieved by using paralleled PMOS and NMOS differential input stages. (See Simplified
Schematic in this datasheet). When the common mode input voltage changes from ground to the positive rail, the
input stage goes through three modes. First, the NMOS pair is cutoff and the PMOS pair is active. At around
1.4V, both PMOS and NMOS pairs operate, and finally the PMOS pair is cutoff and NMOS pair is active. Since
both input stages have their own offset voltage (V
OS
), the offset of the amplifier becomes a function of the
common-mode input voltage. See curves for V
OS
vs. V
CM
in Typical Performance Characteristics section.
As shown in the curve, the V
OS
has a crossover point at 1.4V above V
−
. Proper design must be done in both DC
and AC coupled applications to avoid problems. For large input signals that include the V
OS
crossover point in
their dynamic range, it will cause distortion in the output signal. One way to avoid such distortion is to keep the
signal away from the crossover point. For example, in a unity gain buffer configuration and with V
S
= 5V, a 3V
peak-to-peak signal center at 2.5V will contain input-crossover distortion. To avoid this, the input signal should be
centered at 3.5V instead. Another way to avoid large signal distortion is to use a gain of −1 circuit which avoids
any voltage excursions at the input terminals of the amplifier. See Figure 36. In this circuit, the common mode
DC voltage (V
CM
) can be set at a level away from the V
OS
crossover point.
Figure 36.
When the input is a small signal and this small signal falls inside the V
OS
transition range, the gain, CMRR and
some other parameters will be degraded. To resolve this problem, the small signal should be placed such that it
avoids the V
OS
crossover point.
To achieve maximum output swing, the output should be biased at mid-supply. This is normally done by biasing
the input at mid-supply. But with supply voltage range from 2V to 3.4V, the input of the op amp should not be
biased at mid-supply because of the transition of the V
OS
. Figure 37 shows an example of how to get away from
the V
OS
crossover point and maintain a maximum swing with a 2.7V supply. Figure 38 shows the waveforms of
V
IN
and V
OUT
.
12 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: LMV710-N LMV711-N LMV715-N