Datasheet

C
F
=
¨
¨
©
§
R
F
+ 2R
IN
R
F
2
¨
¨
©
§
C
L
R
OUT
R
S
= R
OUT
R
IN
R
F
R
OUT
-
+
V
IN
R
F
C
F
R
IN
R
L
C
L
R
S
LMV641
SNOSAW3C –SEPTEMBER 2007–REVISED FEBRUARY 2013 www.ti.com
An op amp, ideally, has a dominant pole close to DC which causes its gain to decay at the rate of 20 dB/decade
with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until
the op amp's unity gain bandwidth, then the op amp is stable. If, however, a large capacitance is added to the
output of the op amp, it combines with the output impedance of the op amp to create another pole in its
frequency response before its unity gain frequency (Figure 40). This increases the ROC to 40 dB/decade and
causes instability.
In such a case, a number of techniques can be used to restore stability to the circuit. The idea behind all these
schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which
ensures stability.
In The Loop Compensation
Figure 41 illustrates a compensation technique, known as in the loop compensation, that employs an RC
feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series
resistance, R
S
, is used to isolate the amplifier output from the load capacitance, C
L
, and a small capacitance, C
F
,
is inserted across the feedback resistor to bypass C
L
at higher frequencies.
Figure 41. In the Loop Compensation
The values for R
S
and C
F
are decided by ensuring that the zero attributed to C
F
lies at the same frequency as the
pole attributed to C
L
. This ensures that the effect of the second pole on the transfer function is compensated for
by the presence of the zero, and that the ROC is maintained at 20 dB/ decade. For the circuit shown in Figure 41
the values of R
S
and C
F
are given by Equation 1. Values of R
S
and C
F
required for maintaining stability for
different values of C
L
, as well as the phase margins obtained, are shown in Table 1. R
F
and R
IN
are 10 kΩ, R
L
is
2 kΩ, while R
OUT
is 680Ω.
(1)
Table 1.
C
L
(nF) R
S
(Ω) C
F
(pF) Phase Margin (°)
0.5 680 10 17.4
1 680 20 12.4
1.5 680 30 10.1
The LMV641 is capable of driving heavy capacitive loads of up to 1 nF without oscillating, however it is
recommended to use compensation should the load exceed 1 nF. Using this methodology will reduce any
excessive ringing and help maintain the phase margin for stability. The values of the compensation network
tabulated above illustrate the phase margin degradation as a function of the capacitive load.
Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth.
The closed loop bandwidth of the circuit is now limited by R
F
and C
F
.
12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMV641