Datasheet

SDA
SCL
1
8
2
3
7
6
5
8
10
4 9
1 7
ack from slave
ack from slave
w rs r stop
ack from slave ack from masterrepeated start data from slave
start
w ack ack rs
r ack ack stop
start
SCL
SDA
MSB Chip Address LSB
slave address =
0011010
2
register address = 0x00h
MSB Register 0x00h LSB
MSB Data LSB
MSB Chip Address LSB
slave address =
0011010
2
register 0x00h data
ack ack ack ack
LMV1089
SNAS441H –SEPTEMBER 2008–REVISED MAY 2010 www.ti.com
Figure 27. Example I
2
C Read Cycle
Figure 28. I
2
C Timing Diagram
Table 4. I
2
C Timing Paramters
(1)
Limit
Symbol Parameter Units
Min Max
1 Hold Time (repeated) 0.6 µs
START Condition
2 Clock Low Time 1.3 µs
3 Clock High Time 600 ns
4 Setup Time for a 600 ns
Repeated START
Condition
5 Data Hold Time (Output 300 1100 ns
direction, delay generated
by LMV1089)
5 Data Hold Time (Input 0 1100 ns
direction, delay generated
by the Master)
6 Data Setup Time 300 ns
7 Rise Time of SDA and 20 300 ns
SCL
8 Fall Time of SDA and SCL 15 300 ns
9 Set-up Time for STOP 600 ns
condition
10 Bus Free Time between a 1.3 µs
STOP and a START
Condition
C
b
Capacitive Load for Each
10 200 pF
Bus Line
(1) Data specified by design
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