Datasheet

SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
LMV1089
SNAS441H –SEPTEMBER 2008–REVISED MAY 2010 www.ti.com
Unprocessed Output Pins
The LMV1089 provides two single ended output pins M1_UNP and M2_UNP. These pins provide the amplified
output signal from the two differential microphone input amplifiers Mic1 and Mic2. When the application
containing the LMV1089 is in a calibrated state the output level of the two microphone paths are matched. This
makes these outputs suitable for stereo applications like video camera webcams and photo cameras. Low cost
microphones with wider gain tolerance can be used because gain differences of the microphones will be
compensated by the calibration system of the LMV1089. In this situation the default gain of the Pre Amplifiers is
set by GA0 and GA1 as described in Table 1. This gain can be changed via I
2
C by writing register A as
described in the I2C Compatible Interface section.
I
2
C Compatible Interface
I
2
C SIGNALS
The LMV1089 pin Serial Clock (SCL) pin is used for the I
2
C clock and the Serial Data (SDA) pin is used for the
I
2
C data. Both these signals need a pull-up resistor according to I
2
C specification. The LMV1089 can be
controlled through two slave addresses. The digital I
2
C address pin selects the I
2
C address for LMV1089 as
shown inTable 3 .
Table 3. Chip Address
D7 D6 D5 D4 D3 D2 D1 D0
1
st
Chip Address
1 1 0 0 1 1 0 W/R
I
2
C Adress='0'
2
nd
Chip Address
1 1 0 0 1 1 1 W/R
I
2
C Adress='1'
I
2
C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line can only be changed when SCL is LOW.
Figure 23. I
2
C Signals: Data Validity
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I
2
C data transmission session. START condition
is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined
as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I
2
C master always generates START and
STOP bits. The I
2
C bus is considered to be busy after START condition and free after STOP condition. During
data transmission, I
2
C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
16 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Links: LMV1089