Datasheet

A
B
C
1 2
D
GND
GND
SW
VOUT
VIN
EN
A
B
C
1 2
VREF
FB
D
LMR70503
SNVS850A –JUNE 2012–REVISED APRIL 2013 www.ti.com
Connection Diagram
Figure 3. LMR70503 Bump Locations - Top View
Figure 4. LMR70503 Package Marking - Top View
(Diamond Denotes Bump A1)
PIN DESCRIPTIONS
Pin Number Name Description
A1 VREF Reference voltage output; connect to the bottom feedback resistor.
Active high enable input for the device. Enable voltage level is referred to GND. Device must be enabled only
B1 EN with the presence of valid VIN (2.8 V to 5.5 V). The peak of the Enable input voltage must always lower than
VIN voltage.
C1, C2 GND Analog ground for internal bias circuitry.
Switch node pin, connected to the internal high side MOSFET. The cathode of the external Schottky diode
D1 SW must be connected as close as possible to this pin, in order to reduce inductance in the discontinuous current
path.
FB is connected to VOUT and VREF through two feedback resistors. It is compared to GND to regulate the
A2 FB
output voltage.
Output voltage. The anode of the external Schottky diode and output filter capacitor(s) should be connected to
B2 VOUT
this pin.
D2 VIN Power supply input pin, connected to the internal high side MOSFET and powers the internal circuity.
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