Datasheet

LMR64010
www.ti.com SNVS736B –SEPTEMBER 2011–REVISED APRIL 2013
The equation shown to calculate maximum load current takes into account the losses in the inductor or turn-OFF
switching losses of the FET and diode. For actual load current in typical applications, we took bench data for
various input and output voltages and displayed the maximum load current available for a typical device in graph
form:
Figure 21. Max. Load Current vs V
IN
DESIGN PARAMETERS V
SW
AND I
SW
The value of the FET "ON" voltage (referred to as V
SW
in the equations) is dependent on load current. A good
approximation can be obtained by multiplying the "ON Resistance" of the FET times the average inductor
current.
FET on resistance increases at V
IN
values below 5V, since the internal N-FET has less gate voltage in this input
voltage range (see Typical Performance Characteristics curves). Above V
IN
= 5V, the FET gate voltage is
internally clamped to 5V.
The maximum peak switch current the device can deliver is dependent on duty cycle. The minimum value is
specified to be > 1A at duty cycle below 50%. For higher duty cycles, see Typical Performance Characteristics
curves.
THERMAL CONSIDERATIONS
At higher duty cycles, the increased ON time of the FET means the maximum output current will be determined
by power dissipation within the LMR64010 FET switch. The switch power dissipation from ON-state conduction is
calculated by:
P
(SW)
= DC x I
IND
(AVE)
2
x R
DS
ON (11)
There will be some switching losses as well, so some derating needs to be applied when calculating IC power
dissipation.
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