Datasheet

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Control
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tO
V
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tC
I
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tL
I
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tL
V
1
D
1
Q
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tSW
V
1
C
1
L
IN
V
LMR62421
www.ti.com SNVS734B –OCTOBER 2011–REVISED APRIL 2013
APPLICATION INFORMATION
THEORY OF OPERATION
The following operating description of the LMR62421 will refer to the Simplified Block Diagram (Figure 12) the
simplified schematic (Figure 13), and its associated waveforms (Figure 14). The LMR62421 supplies a regulated
output voltage by switching the internal NMOS control switch at constant frequency and variable duty cycle. A
switching cycle begins at the falling edge of the reset pulse generated by the internal oscillator. When this pulse
goes low, the output control logic turns on the internal NMOS control switch. During this on-time, the SW pin
voltage (V
SW
) decreases to approximately GND, and the inductor current (I
L
) increases with a linear slope. I
L
is
measured by the current sense amplifier, which generates an output proportional to the switch current. The
sensed signal is summed with the regulator’s corrective ramp and compared to the error amplifier’s output, which
is proportional to the difference between the feedback voltage and V
REF
. When the PWM comparator output goes
high, the output switch turns off until the next switching cycle begins. During the switch off-time, inductor current
discharges through diode D1, which forces the SW pin to swing to the output voltage plus the forward voltage
(V
D
) of the diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage .
Figure 13. Simplified Schematic
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