Datasheet

D
D
'
=
( )
V
o
V
IN
D
D
V
'
C1
=
( )
V
o
2
AREA
1
AREA
S
T
S
DT
( )
tL
V
(s)
t
I
R
V
O
L2
=
x
=
R
¸
¹
·
V
O
¨
©
§
¨
©
§
D
D
'
¸
¹
·
I
L1
=
and
L2
I
x
L1
I
D
¸
¹
·
¨
©
§
'
D
LMR62421
www.ti.com SNVS734B –OCTOBER 2011–REVISED APRIL 2013
Small ripple approximation:
In a well-designed SEPIC converter, the output voltage, and input voltage ripple, the inductor ripple and is small
in comparison to the DC magnitude. Therefore it is a safe approximation to assume a DC value for these
components. The main objective of the Steady State Analysis is to determine the steady state duty-cycle, voltage
and current stresses on all components, and proper values for all components.
In a steady-state converter, the net volt-seconds across an inductor after one cycle will equal zero. Also, the
charge into a capacitor will equal the charge out of a capacitor in one cycle.
Therefore:
(19)
Substituting I
L1
into I
L2
(20)
The average inductor current of L2 is the average output load.
Figure 20. Inductor Volt-Sec Balance Waveform
Applying Charge balance on C1:
(21)
Since there are no DC voltages across either inductor, and capacitor C6 is connected to Vin through L1 at one
end, or to ground through L2 on the other end, we can say that
V
C1
= V
IN
(22)
Therefore:
(23)
This verifies the original conversion ratio equation.
It is important to remember that the internal switch current is equal to I
L1
and I
L2
. During the D interval. Design
the converter so that the minimum ensured peak switch current limit (2.1A) is not exceeded.
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