Datasheet

0
0
V
IN
V
D
T
ON
t
t
Inductor
Current
D = T
ON
/T
SW
V
SW
T
OFF
T
SW
I
L
I
PK
SW
Voltage
LMR10515
www.ti.com SNVS728C –OCTOBER 2011–REVISED APRIL 2013
APPLICATIONS INFORMATION
THEORY OF OPERATION
The following operating description of the LMR10515 will refer to the Simplified Block Diagram Figure 20 and to
the waveforms in Figure 21. The LMR10515 supplies a regulated output voltage by switching the internal PMOS
control switch at constant frequency and variable duty cycle. A switching cycle begins at the falling edge of the
reset pulse generated by the internal oscillator. When this pulse goes low, the output control logic turns on the
internal PMOS control switch. During this on-time, the SW pin voltage (V
SW
) swings up to approximately V
IN
, and
the inductor current (I
L
) increases with a linear slope. I
L
is measured by the current sense amplifier, which
generates an output proportional to the switch current. The sense signal is summed with the regulator’s
corrective ramp and compared to the error amplifier’s output, which is proportional to the difference between the
feedback voltage and V
REF
. When the PWM comparator output goes high, the output switch turns off until the
next switching cycle begins. During the switch off-time, inductor current discharges through the Schottky catch
diode, which forces the SW pin to swing below ground by the forward voltage (V
D
) of the Schottky catch diode.
The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage.
Figure 21. Typical Waveforms
SOFT-START
This function forces V
OUT
to increase at a controlled rate during start up. During soft-start, the error amplifier’s
reference voltage ramps from 0V to its nominal value of 0.6V in approximately 600 µs. This forces the regulator
output to ramp up in a controlled fashion, which helps reduce inrush current.
OUTPUT OVERVOLTAGE PROTECTION
The over-voltage comparator compares the FB pin voltage to a voltage that is 15% higher than the internal
reference V
REF
. Once the FB pin voltage goes 15% above the internal reference, the internal PMOS control
switch is turned off, which allows the output voltage to decrease toward regulation.
UNDERVOLTAGE LOCKOUT
Under-voltage lockout (UVLO) prevents the LMR10515 from operating until the input voltage exceeds 2.73V
(typ). The UVLO threshold has approximately 430 mV of hysteresis, so the part will operate until V
IN
drops below
2.3V (typ). Hysteresis prevents the part from turning off during power up if V
IN
is non-monotonic.
CURRENT LIMIT
The LMR10515 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a
current limit comparator detects if the output switch current exceeds 2.5A (typ), and turns off the switch until the
next switching cycle begins.
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