Datasheet

cv
+
-
+
-
S
R
R
Q
+
-
GND
FB
SW
VIN
EN
+
-
+
-


DRIVER
Artificial
Ramp
SHDN
Thermal
SHDN
OVP
1.6 MHz
CompInternal -
SENSE
I
LIMIT
I
LDOInternal -
STARTSOFT-
PFET
SENSE
I
ENABLE and UVLO
15.1 x
REF
V
Control Logic
V
REF
= 0.6V
LMR10510
SNVS727B –OCTOBER 2011–REVISED APRIL 2013 www.ti.com
Simplified Block Diagram
Figure 20.
APPLICATIONS INFORMATION
THEORY OF OPERATION
The following operating description of the LMR10510 will refer to the Simplified Block Diagram (Figure 20) and to
the waveforms in Figure 21. The LMR10510 supplies a regulated output voltage by switching the internal PMOS
control switch at constant frequency and variable duty cycle. A switching cycle begins at the falling edge of the
reset pulse generated by the internal oscillator. When this pulse goes low, the output control logic turns on the
internal PMOS control switch. During this on-time, the SW pin voltage (V
SW
) swings up to approximately V
IN
, and
the inductor current (I
L
) increases with a linear slope. I
L
is measured by the current sense amplifier, which
generates an output proportional to the switch current. The sense signal is summed with the regulator’s
corrective ramp and compared to the error amplifier’s output, which is proportional to the difference between the
feedback voltage and V
REF
. When the PWM comparator output goes high, the output switch turns off until the
next switching cycle begins. During the switch off-time, inductor current discharges through the Schottky catch
diode, which forces the SW pin to swing below ground by the forward voltage (V
D
) of the Schottky catch diode.
The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage.
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