Datasheet

S A[6:0] W A BLK0 PA D[7:0] A AD[7:0]
24 bytes of Data
by master
by slave
Block
Command
Interface
Address
S A[6:0] W A BLK0 A[6:0] R A D[7:0] PA AD[7:0]A
24 bytes of Data
by master
by slave
Sr
Interface
Address
Interface
Address
Block
Command
LMP92001
www.ti.com SNAS507B –FEBRUARY 2011–REVISED APRIL 2012
Figure 26. Block Command READ Access
Figure 27. Block Command WRITE Access
I
2
C-Compatible Bus Reset
In cases where Master and Slave interfaces fall out of synchronization there are 2 processes which can reset the
Slave and return it to a known state:
• TIMEOUT: The device will automatically reset its interface and wait for a new START condition (by the
Master) if SCL is driven LOW for duration longer than t
OUT
(see Electrical Characteristics Table), or SDA is
driven LOW by this device for duration longer than t
OUT
. The TIMEOUT feature can be disabled by the user,
see CGEN register functionality.
• When SDA is in HIGH state, the Master can issue START condition at any time. The START condition resets
the Slave interface, and Slave expects to see Interface Address byte next.
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