Datasheet

A6 AR/WA0A1A2A3A4A5S
by master
by slave
S A[6:0] W A PA D[7:0] A AD[7:0]
Data
Internal
Register
Address
by slave
Ar[7:0]
Interface
Address
LMP92001
SNAS507B –FEBRUARY 2011–REVISED APRIL 2012 www.ti.com
Figure 24. I
2
C-Compatible WRITE Access Protocol
Device Address
Interface Address of the device can be set via 2 pins: AS0 and AS1. Each address setting pin recognizes 3
levels: LOW=GND, HIGH=VDD and MID=VDD/2. All possible Interface Addresses are listed in Table 3 below:
Table 3. Interface Address Space
Device Pins
Device Interface Address
Equivalent HEX Address
[A6:A0]R/W
AS1 AS0
LOW LOW [0100 000]0 40
LOW MID [0100 001]0 42
LOW HIGH [0100 010]0 44
MID LOW [0100 011]0 46
MID MID [0100 100]0 48
MID HIGH [0100 101]0 4A
HIGH LOW [0100 110]0 4C
HIGH MID [0100 111]0 4E
HIGH HIGH [0101 000]0 50
The Interface Address alignment within the I
2
C-compatible address byte is shown in Figure 25 below:
Figure 25. Interface Address Sequence within the I
2
C-Compatible Frame
Block Access
Block Access functionality minimizes overhead in bus transfers involving larger data sets (more than 2 bytes).
Internal register addresses 0xF0 through 0xF5 are interpreted by the interface as block commands. Accessing
any of these addresses initiates a multi-byte transfer which can be as long as 34 data bytes. The byte length of
the transfer is dictated by the block command itself. Examples of access to internal register at address 0xF0 is
shown in Figure 26 and Figure 27.
BLK0 command is issued meaning that all DACx registers accessed are accessed sequentially.
The transfer will consist of 24 bytes – 2 bytes per DACx register.
The data WRITE transfers that terminate prematurely will result in update of registers whose 16-bit words were
received completely. For example, if BLK0 WRITE access is attempted, and the transfer is terminated after 3
bytes, only DAC1 register will be updated.
30 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: LMP92001