Datasheet

S A[6:0] W A Ar[7:0] A[6:0] R A D[7:0] PA AD[7:0]A
Data
by master
by slave
Interface
Address
Internal
Register
Address
Interface
Address
Sr
CA5 A1 A0A6 D7 D0
1 2 6 7 8 9 1 8 9
S
P
SDA
SCL
R/W A/A A/A
Start Stop
D0
8 9
A/A
Repeated
Start
Sr
Slave Address Byte
Data Byte
by master
by slave
by master or by slave
LMP92001
www.ti.com SNAS507B –FEBRUARY 2011–REVISED APRIL 2012
Figure 22. General I
2
C-Compatible Protocol
Table 2 lists all conditions defined by the I
2
C-compatible specification and supported by this device. All following
bus descriptions will refer to the Symbols listed in the table.
Table 2. I
2
C-Compatible Symbol Set
Condition Symbol Source Description
START S Master Begins all bus transactions
STOP P Master Terminates all transactions, and resets bus
ACK
A Master/Slave Handshaking bit (LOW)
(Acknowledge)
NAK
A Master/Slave Handshaking bit (HIGH)
(No Acknowledge)
Active HIGH bit that follows immediately after the slave
READ R Master address sequence. Indicates that the master is initiating
the slave to master data transfer
Active LOW bit that follows immediately after the slave
WRITE W Master address sequence. Indicates that the master is initiating
the master to slave data transfer
Generated by master, same function as the Start
REPEATED START Sr Master condition (highlights the fact that Stop condition is not
strictly necessary)
Data transfers of 16-bit values are shown in Figure 23 and Figure 24 below:
Figure 23. I
2
C-Compatible READ Access Protocol
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