Datasheet

CGPO GPOx

Device Pin

GPIOx

SGPI GPIx

LMP92001

SNAS507B –FEBRUARY 2011–REVISED APRIL 2012

www.ti.com

Figure 21. GPIO Functionality

SERIAL INTERFACE

The serial interface provides user access to internal CONTROL and DATA registers that govern the operation of

the device. Interface functionality is compatible with I

C “Standard” and “Fast” modes.

The device operates as the slave only.

C-Compatible Protocol

Two wires, SCL and SDA, are used to carry data between master (the digital supervisor), and a slave

(LMP92001). Master generates a START condition which commences all data transfers. And only the master

generates the SCL signal for all transactions. However, both master and the slave can in turn be a transmitter

and receiver of data.

Typical bus transaction is shown in Figure 22 below. All transactions follow the format outlined as follows:

• Master begins all transactions by generating START condition

• All transfers comprise 8-bit bytes

• First byte must contain 7-bit Slave Interface Address

• First byte is followed by a READ/WRITE bit

• All subsequent bytes contain 8-bit data

• Device, depending on the register being accessed, supports 1-byte and 2-byte transfers. Block Access

commands result in multi-byte transfers

• In case of a 2-byte transfers, the byte order is always “MSB first”

• Bit order within byte is always “MSB” first”

• ACKNOWLEDGE condition follows every byte transfer – this can be generated by either Master or a Slave

depending on the direction of data transfer

Product Folder Links: LMP92001