Datasheet

CREF DEXTAEXT
DREF
Register bit
Register
Device Pin
AREF
0
1
0
1
x1
x1
Reference
Block
To ADC
VREF
input
To DACx
VREF
inputs
PD
LMP92001
www.ti.com SNAS507B –FEBRUARY 2011–REVISED APRIL 2012
NOTE
Internal reference drive must be disabled when corresponding external reference is
applied; e.g., set CREF.AEXT=1 when applying external AREF.
Figure 20. Reference Select Function
GENERAL PURPOSE I/O
The GPIO[7:0] port is memory mapped to registers SGPI and CGPO. Both registers are accessible through the
I
2
C-compatible interface.
The SGPI register content reflects at all times the digital state at the GPIOx device pins.
The CGPO register controls the individual pulldown devices at GPIOx. Together with the external pull-up resistor
this realizes an “open-drain” digital output. For example, writing HIGH to CGPO:GPO0 will result in HIGH output
state at pin GPIO0.
The functional diagram of the GPIO subcircuit is shown in Figure 21.
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