Datasheet

VOUTx = VREF x
DACx
4096
R
R
R
R
R
DECODER
w(R) = 120k
VDD
Buffer
1
0
VREF
PD
VOUTx
DACx
12
LMP92001
www.ti.com SNAS507B –FEBRUARY 2011–REVISED APRIL 2012
Figure 18. DAC Core
Typical DAC core output VOUTx as a function of the DACx input , x=1...12, can be expressed as:
Reference
By default the DACs operate from the external reference voltage applied at the DREF pin of the device. Given
the architecture of the DAC the DC current flowing into the DREF device input pin is dependent on the number of
DACs active at the given instant.
The user can enable the internal reference generator and apply its output to all DACs’ VREF inputs. This
operation is described in ADC/DAC VOLTAGE REFERENCE.
Asynchronous Output Control
When DACs are enabled, CDAC.OFF=0, the Cy device inputs allow the user to instantaneously disengage the
VOUTx of corresponding DAC Core and force the OUTx to either rail – the rail is indicated by the CDAC.OLVL
bit. Asserting either CDAC.OFF or Cy (Active LOW) will result in the corresponding DAC Core powering down.
The functional diagram of the DAC Core to OUTx signal routing is shown in Figure 19.
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