Datasheet

CINH

CINL

EHx

ELy

INT1

INT2

Device Pin

SHIL Hx

SLOL Ly

x=1..3

CINH

CINL

EHx

ELy

SHIL Hx

SLOL Ly

y=1..3

x=9..11

y=9..11

LMP92001

SNAS507B –FEBRUARY 2011–REVISED APRIL 2012

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Figure 17. Interrupt System

PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM

This subsystem consists of 12 identical DACs whose output is a function of user programmable registers DACx.

This functionality is described in DAC Core.

There are instances where it is necessary to instantaneously “turn off” the devices downstream of OUTx output,

without incurring the delay due to the I

C-compatible data/command transfer. This functionality is described in

Asynchronous Output Control.

DAC Core

The DAC core is based on a Resistive String architecture which specifies monotonicity of its transfer function.

The input data is single-registered, meaning that the VOUTx of the DAC is updated as soon as the data is

updated in the DACx data register at the end of the I

C-compatible transaction.

The functional diagram of the DAC Core is shown in Figure 18.

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