Datasheet

ADC
IDLE
CGEN.LCK==1
set SGEN.BUSY=1
x=0
x=x+1
CAD(1|2|3).ENx==1
set analog input
MUX to channel x
update ADCx
register
x==17
set SGEN.BUSY=0
Write CGEN.STRT=1
Write CTRIG while CGEN.STRT=0
Y
Y
N
N
Y
N
acquire signal
t
TRACK
period
convert input signal
t
HOLD
period
LMP92001
SNAS507B –FEBRUARY 2011–REVISED APRIL 2012 www.ti.com
Figure 15. ADC Finite State Machine Diagram
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