Datasheet

LMP92001
SNAS507B –FEBRUARY 2011–REVISED APRIL 2012 www.ti.com
Bx Name Function
5 EL11 1 - Enable Low limit interrupt for Ch 11
4 EL10 1 - Enable Low limit interrupt for Ch 10
3 EL9 1 - Enable Low limit interrupt for Ch 9
2 EL3 1 - Enable Low limit interrupt for Ch 3
1 EL2 1 - Enable Low limit interrupt for Ch 2
0 EL1 1 - Enable Low limit interrupt for Ch 1
ADC Conversion Enable Register 1: CAD1[7:0], default = 0x00
Bx Name Function
7 EN8 1 - Enable ADC input Ch 8
6 EN7 1 - Enable ADC input Ch 7
5 EN6 1 - Enable ADC input Ch 6
4 EN5 1 - Enable ADC input Ch 5
3 EN4 1 - Enable ADC input Ch 4
2 EN3 1 - Enable ADC input Ch 3
1 EN2 1 - Enable ADC input Ch 2
0 EN1 1 - Enable ADC input Ch 1
ADC Conversion Enable Register 2: CAD2[7:0], default = 0x00
Bx Name Function
7 EN16 1 - Enable ADC input Ch 16
6 EN15 1 - Enable ADC input Ch 15
5 EN14 1 - Enable ADC input Ch 14
4 EN13 1 - Enable ADC input Ch 13
3 EN12 1 - Enable ADC input Ch 12
2 EN11 1 - Enable ADC input Ch 11
1 EN10 1 - Enable ADC input Ch 10
0 EN9 1 - Enable ADC input Ch 9
ADC Conversion Enable Register 3: CAD3[7:0], default = 0x00
Bx Name Function
7:1 - RESERVED
0 EN17 1 - Enable Temp Sensor ADC input channel
ADC One-Shot Conversion Trigger Register : CTRIG[7:0], default = 0x00
Bx Name Function
7:1 - RESERVED
Writing any value, when CGEN.STRT=0, will trigger Single-Shot conversion. The CGEN.LCK bit
0 SNGL
must be set for the conversion sequence to begin.
Reference Mode Register: CREF[7:0], default = 0x07
Bx Name Function
7:3 - RESERVED
1 - ADC external ref. enable
2 AEXT
0 - ADC internal ref. enable
1 - DAC external ref. enable
1 DEXT
0 - DAC internal ref. enable
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