Datasheet
LMP92001
www.ti.com
SNAS507B –FEBRUARY 2011–REVISED APRIL 2012
CONTROL REGISTERS
General Configuration Register: CGEN[7:0], default = 0x00
Bx Name Function
7 RST 1 - RESETS all registers and self to POR value
6:3 - RESERVED
2 TOD 1 - disable I
2
C-compatible TIMEOUT. See I
2
C-Compatible Bus Reset
1 - to lock registers. Lockable registers are shown in the REGISTER MAP. Once locked
1 LCK
their contents will not be affected by the subsequent I
2
C-compatible bus transactions
1 - to start continuous conversion of all enabled ADC channels. The CGEN.LCK bit must
0 STRT be set for the conversion sequence to begin
0 - disable continuous ADC conversion mode
DAC Configuration Register: CDAC[7:0], default 0x03
Bx Name Function
7:3 - RESERVED
Controls the association of analog output channels OUTx with asynchronous control inputs
2 GANG
Cy. (See Asynchronous Output Control)
1 - Cy=0 will force associated OUTx outputs to VDD
1 OLVL
0 - Cy=0 will force associated OUTx outputs to GND
0 OFF 1 - forces all OUT[1:12] outputs to HIGH impedance state
GPIO Output Control Register: CGPO[7:0], default = 0xFF
Bx Name Function
7 GPO7 1 - Internal pulldown at pin GPIO7 is off
6 GPO6 1 - Internal pulldown at pin GPIO6 is off
5 GPO5 1 - Internal pulldown at pin GPIO5 is off
4 GPO4 1 - Internal pulldown at pin GPIO4 is off
3 GPO3 1 - Internal pulldown at pin GPIO3 is off
2 GPO2 1 - Internal pulldown at pin GPIO2 is off
1 GPO1 1 - Internal pulldown at pin GPIO1 is off
0 GPO0 1 - Internal pulldown at pin GPIO0 is off
INT1, INT2 High-Limit Control Register: CINH[7:0], default = 0x00
Bx Name Function
7 - RESERVED
6 - RESERVED
5 EH11 1 - Enable High limit interrupt for Ch 11
4 EH10 1 - Enable High limit interrupt for Ch 10
3 EH9 1 - Enable High limit interrupt for Ch 9
2 EH3 1 - Enable High limit interrupt for Ch 3
1 EH2 1 - Enable High limit interrupt for Ch 2
0 EH1 1 - Enable High limit interrupt for Ch 1
INT1, INT2 Low-Limit Control Register: CINL[7:0], default = 0x00
Bx Name Function
7 - RESERVED
6 - RESERVED
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