Datasheet

LMP92001
www.ti.com SNAS507B –FEBRUARY 2011–REVISED APRIL 2012
Addr. Name Function R/W Lock
0x41 LIH2 ADC Ch2 HIGH limit RW Y
0x42 LIH3 ADC Ch3 HIGH limit RW Y
0x43 LIH9 ADC Ch9 HIGH limit RW Y
0x44 LIH10 ADC Ch10 HIGH limit RW Y
0x45 LIH11 ADC Ch11 HIGH limit RW Y
0x46 LIL1 ADC Ch1 LOW limit RW Y
0x47 LIL2 ADC Ch2 LOW limit RW Y
0x48 LIL3 ADC Ch3 LOW limit RW Y
0x49 LIL9 ADC Ch9 LOW limit RW Y
0x4A LIL10 ADC Ch10 LOW limit RW Y
0x4B LIL11 ADC Ch11 LOW limit RW Y
INTERNAL REFERENCE CONTROL
0x66 CREF Int. reference enable RW
DAC INPUT DATA
0x80 DAC1 DAC Ch1 Input Data RW
0x81 DAC2 DAC Ch2 Input Data RW
0x82 DAC3 DAC Ch3 Input Data RW
0x83 DAC4 DAC Ch4 Input Data RW
0x84 DAC5 DAC Ch5 Input Data RW
0x85 DAC6 DAC Ch6 Input Data RW
0x86 DAC7 DAC Ch7 Input Data RW
0x87 DAC8 DAC Ch8 Input Data RW
0x88 DAC9 DAC Ch9 Input Data RW
0x89 DAC10 DAC Ch10 Input Data RW
0x8A DAC11 DAC Ch11 Input Data RW
0x8B DAC12 DAC Ch12 Input Data RW
0x8C
| RESERVED
0x8F
0x90 DALL All DAC Data W
MEMORY MAPPED BLOCK COMMANDS
0xF0 BLK0 DAC1-12 access RW
0xF1 BLK1 DAC7-12 access RW
0xF2 BLK2 ADC1-17 access R
0xF3 BLK3 ADC9-17 access R
0xF4 BLK4 LIHx, LILx access RW
0xF5 BLK5 LILx access RW
0xF6
| RESERVED
0xFF
TEST AND INFO REGISTERS
The registers in this section do not affect the operation of the device. They are provided for user convenience
and product identification.
Test Register: TEST[7:0], default = 0x00
This register can be used for verification of the I
2
C-compatible bus integrity. Its contents are ignored by the
device.
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