Datasheet

LMP92001
SNAS507B –FEBRUARY 2011–REVISED APRIL 2012 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, these specifications apply for VDD=4.75V to 5.5V, AREF=DREF=VDD, T
A
=25°C. Boldface limits are
over the temperature range of −40°C ≤ T
A
≤ 125°C unless otherwise noted. DAC input code range 48 to 4047. DAC output C
L
= 200 pF unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
DIGITAL OUTPUT CHARACTERISTICS (SDA)
V
OL
Output LOW Voltage I
OUT
= 4mA 0.16 0.4 V
I
OUT
= 6mA 0.23 0.6 V
DIGITAL OUTPUT CHARACTERISTICS (All Outputs)
Current from the supply rail through
I
OL
Output Leakage when HIGH the pullup resistor into the drain of ±1 µA
the open-drain output device
C
OUT
Output Capacitance Force 0V or VDD 4 pF
POWER SUPPLY CHARACTERISTICS
V
DD
Supply Voltage Range 4.75 5 5.5 V
Supply Current, converting, all
I
DD
OUT[1:12] pins R
L
= ∞ 4 6.5 mA
blocks active
Power Consumption, converting, all
PWR OUT[1:12] pins R
L
= ∞ 25 36 mW
blocks active
−40°C ≤ T
A
≤ 105°C 1.9 2.4
V
POR
Power-On Reset
(2)
V
1.85 2.45
AC ELECTRICAL CHARACTERISTICS
Interval during which internal HOLD
t
TRACK
ADC Track Time capacitor is connected to input 4.7 5.3 µs
signal
Interval during which sampled signal
t
HOLD
ADC Hold Time 3.3 3.8 µs
is converted to digital output code
400h to C00h code change, R
L
= 2k
t
s
DAC Settling Time
(3)
6 8.5 µs
C
L
= 200 pF
I
2
C TIMING CHARACTERISTICS
I
2
C Clock Frequency 10 400 kHz
t
LOW
Clock Low Time 1.3 µs
t
HIGH
Clock High Time 0.6 µs
Hold Time Repeated START After this period, the first clock pulse
t
HD;STA
0.6 µs
condition is generated
Set-up time for a repeated START
t
SU;STA
0.6 µs
condition
t
HD;DAT
Data hold time
(4) (5)
0 900 ns
t
SU;DAT
Data setup time 100 ns
t
f
SDA fall time I
L
≤ 3mA and C
L
≤ 400 pF 250 ns
t
SU;STO
Set-up time for STOP condition 0.6 µs
Bus free time between a STOP and
t
BUF
1.3 µs
START condition
C
b
SDA capacitive load 400 pF
Pulse width of spikes that must be
t
SP
50 ns
suppressed by the input filter
t
OUT
SCL and SDA Timeout 25 35 ms
(2) During the power up the supply rail must ramp up beyond V
POR
MIN for the device to acquire default state. After the supply rail has
reached the nominal level, the rail can drop as low as V
POR
MAX for the current state to be maintained.
(3) Device Specification is ensured by characterization and is not tested in production.
(4) Data hold time is measured from the falling edge of SCL, applies to data transmission and the acknowledge.
(5) Device internally provides a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.
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