Datasheet

50%
VCMHI
SDO_DIAG
90%
10%
90%
10%
90%
10%
T1
90%
10%
50% 50% 50%
T2 T3
90%
10%
CSB
DIAG_t
F
DIAG_t
R
DIAG_t
ON
VCM_DIAG_t
F
VCM_DIAG_t
R
DIAG_t
SET
t
7
t
8
t
3
t
2
t
1
t
4
t
5
t
6
D
15
D
0
D
14
SCLK
SDO_DIAG
SDI
CSB
OLD D
15
t
9
OLD D
1
OLD D
0
t
R
90%
10%
t
F
90%
10%
LMP91200
SNAS571C –JANUARY 2012–REVISED MARCH 2013 www.ti.com
TEST CIRCUIT DIAGRAMS
Figure 2. SERIAL INTERFACE TIMING DIAGRAM
Figure 3. DIAGNOSTIC TIMING DIAGRAM
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