Datasheet

LMP91200
SNAS571C –JANUARY 2012–REVISED MARCH 2013 www.ti.com
Electrical Characteristics
(1)(2)(3)
(continued)
Unless otherwise specified, all limits specified for T
A
= 25°C. V
S
=(VDD-GND)=3.3V. VREF=3.3V. Boldface limits apply at the
temperature extremes.
Symbol Parameter Condition Min
(4)
Typ
(5)
Max
(4)
Units
PGA
-275 275
Vos
PGA
Input Voltage Offset
(17)
+IN_PGA (Internal node) = 500mV µV
-480 480
TcVos
PGA
Input offset voltage drift
(18)(19)
+IN_PGA (Internal node) = 500mV -2.5 2.5 uV/°C
Aol
PGA
Open loop Gain +IN_PGA (Internal node) = 500mV 90 120 dB
5
Av
PGA
Gain Programmable gain V/V
10
Av_acc
PGA
Gain accuracy -1.3 1.3 %
Input referred noise (low
En_RMS
PGA
Integrated 0.1Hz to 10Hz 2.6 µV
PP
frequency)
(18)
Input referred noise (high
en
PGA
f=1KHz 90 nV/√Hz
frequency)
(18)
1.8V<VDD<5V,
PSRR
PGA
DC_Power supply rejection ratio 80 dB
+IN_PGA (Internal node) = 500mV
Sourcing, Vout to GND
10 16
+IN_PGA (Internal node) = 500mV
Isc
PGA
Output short circuit current
(20)
mA
Sinking, Vout to VDD
8 12
+IN_PGA (Internal node) = 500mV
Reference Input
Rin
VREF
Input impedance
(18)
500 KΩ
(17) Boldface limits are production tested at 125°C. Limits are specified through correlations using the Statistical Quality Control (SQC)
method.
(18) This parameter is specified by design and/or characterization and is not tested in production.
(19) Offset voltage average drift is determined by dividing the change in V
OS
at the temperature extremes by the total temperature change.
(20) The short circuit test is a momentary open loop test.
Electrical Characteristics (Serial Interface)
(1)
Unless otherwise specified. All limits specified for T
A
=25°C, V
S
=(VDD-GND)=3.3V.
Symbol Parameter Condition Min
(2)
Typ
(3)
Max
(2)
Units
VIL Logic Low Threshold 0.3XVDD V
VIH Logic High Threshold (SDO pin) 0.7XVDD V
ISDO=100µA 0.2
Output Logic LOW Threshold
VOL V
(SDO pin)
ISDO=2mA 0.4
ISDO=100µA VDD-0.2
VOH Output Logic High Threshold V
ISDO=2mA VDD-04
t1 High Period, SCLK 100 ns
t2 Low Period, SCLK 100 ns
t3 Set Up Time, CSB to SCLK 50 ns
t4 Set Up Time, SDI to SCLK 30 ns
See
(4)
t5 Hold Time,S CLK to SDI 10 ns
t6 Hold Time,SCLK to SDO_DIAG 40 ns
Hold Time, SCLK Transition to
t7 50 ns
CSB Rising Edge
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ >TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) Load for these tests is shown in the timing diagram test circuit.
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