Datasheet

LMP91000
www.ti.com SNAS506H –JANUARY 2011–REVISED MARCH 2013
LOCK -- Protection Register (address 0x01)
The lock bit enables and disables the writing of the TIACN and the REFCN registers. In order to change the
content of the TIACN and the REFCN registers the lock bit needs to be set to “0”.
Bit Name Function
[7:1] RESERVED
Write protection
0 LOCK 0 Registers 0x10, 0x11 in write mode
1 Registers 0x10, 0x11 in read only mode (default)
TIACN -- TIA Control Register (address 0x10)
The parameters in the TIA control register allow the configuration of the transimpedance gain (R
TIA
) and the load
resistance (R
Load
).
Bit Name Function
[7:5] RESERVED RESERVED
TIA feedback resistance selection
000 External resistance (default)
001 2.75kΩ
010 3.5kΩ
[4:2] TIA_GAIN 011 7kΩ
100 14kΩ
101 35kΩ
110 120kΩ
111 350kΩ
R
Load
selection
00 10Ω
[1:0] RLOAD 01 33Ω
10 50Ω
11 100Ω (default)
REFCN -- Reference Control Register (address 0x11)
The parameters in the Reference control register allow the configuration of the Internal zero, Bias and Reference
source. When the Reference source is external, the reference is provided by a reference voltage connected to
the VREF pin. In this condition the Internal Zero and the Bias voltage are defined as a percentage of VREF
voltage instead of the supply voltage.
Bit Name Function
Reference voltage source selection
7 REF_SOURCE 0 Internal (default)
1 external
Internal zero selection (Percentage of the source reference)
00 20%
[6:5] INT_Z 01 50% (default)
10 67%
11 Internal zero circuitry bypassed (only in O
2
ground referred measurement)
Selection of the Bias polarity
4 BIAS_SIGN 0 Negative (V
WE
– V
RE
)<0V (default)
1 Positive (V
WE
–V
RE
)>0V
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