Datasheet

D7 D6 D5 D4 D3 D2 D1 D0
1 9
Ack
by
LMP91000
Start by
Master
No Ack
by
Master
SCL
SDA
Stop
by
Master
1 9
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Data Byte from
Slave
R/W
A2
A0A1
A3A4A5A6
MENB
D7 D6 D5 D4 D3 D2 D1 D0
1 9
1 9
Ack
by
LMP91000
Start by
Master
R/W
Ack
by
LMP91000
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Internal Address Register
Byte from Master
A2
A0A1
A3A4A5A6
SCL
SDA
Stop by
Master
MENB
LMP91000
SNAS506H –JANUARY 2011–REVISED MARCH 2013 www.ti.com
Figure 27. Pointer Set Transaction
Figure 28. Register Read Transaction
TIMEOUT FEATURE
The timeout is a safety feature to avoid bus lockup situation. If SCL is stuck low for a time exceeding t_timeout,
the LMP91000 will automatically reset its I
2
C interface. Also, in the case the LMP91000 hangs the SDA for a time
exceeding t_timeout, the LMP91000’s I
2
C interface will be reset so that the SDA line will be released. Since the
SDA is an open-drain with an external resistor pull-up, this also avoids high power consumption when LMP91000
is driving the bus and the SCL is stopped.
REGISTERS
The registers are used to configure the LMP91000.
If writing to a reserved bit, user must write only 0. Readback value is unspecified and should be discarded.
Table 2. Register map
Address Name Power on default Access Lockable?
0x00 STATUS 0x00 Read only N
0x01 LOCK 0x01 R/W N
0x02 through 0x09 RESERVED
0x10 TIACN 0x03 R/W Y
0x11 REFCN 0x20 R/W Y
0x12 MODECN 0x00 R/W N
0x13 through 0xFF RESERVED
STATUS -- Status Register (address 0x00)
The status bit is an indication of the LMP91000's power-on status. If its readback is “0”, the LMP91000 is not
ready to accept other I
2
C commands.
Bit Name Function
[7:1] RESERVED
Status of Device
0 STATUS 0 Not Ready (default)
1 Ready
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