Datasheet

D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
LMP91000
Start by
Master
R/W
Ack
by
LMP91000
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Internal Address Register
Byte from Master
1 9
Ack
by
LMP91000
Frame 3
Data Byte
D3
D1D2
D4D5D6D7
A2 A0A1A3A4A5A6
SCL
SDA
SCL
(continued)
SDA
(continued)
Stop by
Master
D0
MENB
MENB
(continued)
LMP91000
www.ti.com SNAS506H –JANUARY 2011–REVISED MARCH 2013
V-1399mV=((1154mV - 1399mV)/(50°C -20°C))*(T-20°C)
V-1399mV= -8.16mV/°C*(T-20°C)
V=(-8.16mV/°C)*T+1562.2mV
Using this method of linear approximation, the transfer function can be approximated for one or more
temperature ranges of interest.
I
2
C INTERFACE
The I
2
C compatible interface operates in Standard mode (100kHz). Pull-up resistors or current sources are
required on the SCL and SDA pins to pull them high when they are not being driven low. A logic zero is
transmitted by driving the output low. A logic high is transmitted by releasing the output and allowing it to be
pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and
operating speed. The LMP91000 comes with a 7 bit bus fixed address: 1001 000.
WRITE AND READ OPERATION
In order to start any read or write operation with the LMP91000, MENB needs to be set low during the whole
communication. Then the master generates a start condition by driving SDA from high to low while SCL is high.
The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have been
transmitted by the master, SDA is released by the master and the LMP91000 either ACKs or NACKs the
address. If the slave address matches, the LMP91000 ACKs the master. If the address doesn't match, the
LMP91000 NACKs the master. For a write operation, the master follows the ACK by sending the 8-bit register
address pointer. Then the LMP91000 ACKs the transfer by driving SDA low. Next, the master sends the 8-bit
data to the LMP91000. Then the LMP91000 ACKs the transfer by driving SDA low. At this point the master
should generate a stop condition and optionally set the MENB at logic high level (refer to Figure 26, Figure 27,
and Figure 28).
A read operation requires the LMP91000 address pointer to be set first, also in this case the master needs
setting at low logic level the MENB, then the master needs to write to the device and set the address pointer
before reading from the desired register. This type of read requires a start, the slave address, a write bit, the
address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 26,
Figure 27, and Figure 28). Following this sequence, the LMP91000 sends out the 8-bit data of the register.
When just one LMP91000 is present on the I
2
C bus the MENB can be tied to ground (low logic level).
Figure 26. Register Write Transaction
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