Datasheet

LMP90100
SNAS510P –JANUARY 2011–REVISED MARCH 2013 www.ti.com
Table 18. Default VINx for CH0-CH6
VINP VINN
CH0 VIN0 VIN1
CH1 VIN2 VIN3 (LMP90100/LMP90099 only)
CH2 VIN4 (LMP90100/LMP90099 only) VIN5 (LMP90100/LMP90099 only)
CH3 VIN6 VIN7
CH4 (LMP90100/LMP90099 only) VIN0 VIN1
CH5 (LMP90100/LMP90099 only) VIN2 VIN3
CH6 (LMP90100/LMP90099 only) VIN4 VIN5
Table 19. CHx_CONFIG: Channel Configuration (CH4 to CH6 LMP90100/LMP90099 only)
(1)
Bit Bit Symbol Bit Description
7 Reserved -
ODR Select
0x0: 13.42 / 8 = 1.6775 SPS
0x1: 13.42 / 4 = 3.355 SPS
0x2: 13.42 / 2 = 6.71 SPS
[6:4] ODR_SEL 0x3: 13.42 SPS
0x4: 214.65 / 8 = 26.83125 SPS
0x5: 214.65 / 4 = 53.6625 SPS
0x6: 214.65 / 2 = 107.325 SPS
0x7(default): 214.65 SPS
Gain Select
0x0 (default): 1 (FGA OFF)
0x1: 2 (FGA OFF)
0x2: 4 (FGA OFF)
[3:1] GAIN_SEL 0x3: 8 (FGA OFF)
0x4: 16 (FGA ON)
0x5: 32 (FGA ON)
0x6: 64 (FGA ON)
0x7: 128 (FGA ON)
Enable/Disable the buffer
0 (default): Include the buffer in the signal path
0 BUF_EN
1: Exclude the buffer from the signal path
Note: When gain ≥ 16, the buffer is automatically included in the signal path irrespective of this bit.
(1) Register Address (hex):
(a) CH0: 0x21
(b) CH1: 0x23
(c) CH2: 0x25
(d) CH3: 0x27
(e) CH4: 0x29
(f) CH5: 0x2B
(g) CH6: 0x2D
CALIBRATION REGISTERS
Table 20. BGCALCN: Background Calibration Control (Address 0x10)
Bit Bit Symbol Bit Description
[7:2] Reserved -
Background calibration control – selects scheme for continuous background calibration.
0x0 (default): BgcalMode0: Background Calibration OFF
[1:0] BGCALN 0x1: BgcalMode1: Offset Correction / Gain Estimation
0x2: BgcalMode2: Offset Correction / Gain Correction
0x3: BgcalMode3: Offset Estimation / Gain Estimation
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