Datasheet

R/WB = Read/Write Data
0: Write Data
1: Read Data
7 [3:0] [7:0]
0 0x0
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
[6:5] 4
0 0x3 1000_0010b
Instruction Byte 2 (INST2)
Data Byte (s)
[7:0] [7:3] [2:0]
0x0 0x0
Instruction Byte 1 (INST1)
Upper Address Byte (UAB)
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
0x10
Transaction 2 ± Data Access
Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
LMP90100
SNAS510P –JANUARY 2011–REVISED MARCH 2013 www.ti.com
Figure 68. Setting up SPI_STREAMCN
The next step shows how to perform the Controlled Streaming mode so that the master device will read
ADC_DOUT from ADDR 0x1A, 0x1B, 0x1C, then wrap back to ADDR 0x1A, and repeat this process for four
times. After this process, deassert CSB to end the Controlled Streaming mode.
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