Datasheet

R/WB = Read/Write Data
0: Write Data
1: Read Data
7 [3:0] [23:0]
0 0x2
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
[6:5]
4
0 0xF
The 1
st
Data Byte will be written to ADDR 0x1F, the 2
nd
Data Byte will
be written to ADDR 0x20, and the 3
rd
Data Byte will be written to ADR
0x21. After this process, deassert CSB.
Instruction Byte 2 (INST2)
Data Bytes
[7:0] [7:3] [2:0]
0x0 0x1
Instruction Byte 1 (INST1) Upper Address Byte (UAB)
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
0x10
Transaction 2 ± Data Access
Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
|
- 8,388,608d
1d
ADC_DOUT
- 16, 777, 215d
|
|
VIN
8,388,607d
|
|
-1 LSB
(VREF -1LSB)
+1
LSB
|
(-VREF + 1
LSB)
LMP90100
www.ti.com SNAS510P –JANUARY 2011–REVISED MARCH 2013
Figure 63. ADC_DOUT vs. VIN of a 24-Bit Resolution (VREF = 5.5V, Gain = 1).
REGISTER READ/WRITE EXAMPLES
Writing to Register Examples
Using the register read/write protocol shown in Figure 51, the following example shows how to write three data
bytes starting at register address (ADDR) 0x1F. After the last byte has been written to ADDR 0x21, deassert
CSB to end the register-write.
Figure 64. Register-Write Example 1
The next example shows how to write one data byte to ADDR 0x12. Since the URA for this example is the same
as the last example, transaction 1 can be omitted.
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