Datasheet

Active
Power-downStand-by
PWRCN
= 01b
PWRCN
= 11b
PWRCN
= 00b
PWRCN
= 00b
1/ODR
1/ODR
CH0 CH1
SDO
LSB
Reading
ADC_DOUT of CH0
MSB
MSB
LSB
Reading
ADC_DOUT of CH1
Reading
SPI_CRC_DAT
MSB
MSB
LSB
LSB
Reading
SPI_CRC_DAT
LMP90100
SNAS510P JANUARY 2011REVISED MARCH 2013
www.ti.com
Figure 61. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every
1/ODR seconds
Follow the steps below to enable CRC:
1. Set SPI_CRC_CN = 1 (register 0x13, bit 4) to enable CRC.
2. Set DRDYB_AFT_CRC = 1 (register 0x13, bit 2) to dessert the DRDYB after CRC.
3. Compute the CRC externally, which should include CH_STS, ADC_DOUTH, ADC_DOUTM , and
ADC_DOUTL.
4. Collect the data and verify the reported CRC matches with the computed CRC (step above).
POWER MANAGEMENT
The device can be placed in Active, Power-Down, or Stand-By state.
In Power-Down, the ADC is not converting data, contents of the registers are unaffected, and there is a drastic
power reduction. In Stand-By, the ADC is not converting data, but the power is only slightly reduced so that the
device can quickly transition into the active state if desired.
These states can be selected using the PWRCN register. When written, PWRCN brings the device into the
Active, Power-Down, or Stand-By state. When read, PWRCN indicates the state of the device.
The read value would confirm the write value after a small latency (approximately 15 µs with the internal CLK). It
may be appropriate to wait for this latency to confirm the state change. Requests not adhering to this latency
requirement may be rejected.
It is not possible to make a direct transition from the power-down state to the stand-by state. This state diagram
is shown below.
Figure 62. Active, Power-Down, Stand-by State Diagram
RESET and RESTART
Writing 0xC3 to the REG_AND_CNV_RST field will reset the conversion and most of the programmable registers
to their default values. The only registers that will not be reset are the System Calibration Registers
(CHx_SCAL_OFFSET, CHx_SCAL_GAIN) and the DT_AVAIL_B bit.
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