Datasheet

LMP90100

www.ti.com

SNAS510P –JANUARY 2011–REVISED MARCH 2013

SHORT_THLD_FLAG:

The short circuit threshold flag is used to report a short-circuit condition. It is set when the output voltage (VOUT)

is within the absolute Vthreshold. Vthreshold can be programmed using the 8-bit SENDIAG_THLDH register

concatenated with the 8-bit SENDIAG_THLDL register.

For example, assume VREF = 5V, gain = 1, SENDIAG_THLDH = 0xFA, and SENDIAG_THLDL = 0x45. In this

case, Dthreshold = 0xFA45 = 64069d, and Vthreshold can be calculated as:

Vthreshold = [(Dthreshold)(2)(VREF)] / [(Gain)(2

)] (12)

Vthreshold = [(64069)(2)(5V)] / [(1)(2

)] (13)

Vthreshold = 38.2 mV (14)

When (-38.2mV) ≤ VOUT ≤ (38.2mV), then SHORT_THLD_FLAG = 1; otherwise, SHORT_THLD_FLAG = 0.

RAILS_FLAG:

The rails flag is used to detect if one of the sampled channels is within 50mV of the rails potential (VA or VSS).

This can be further investigated to detect an open-circuit or short-circuit condition. If the sampled channel is near

a rail, then RAILS_FLAG = 1; otherwise, RAILS_FLAG = 0.

POR_AFT_LST_RD:

If POR_AFT_LST_READ = 1, then there was a power-on reset since the last time the SENDIAG_FLAGS register

was read. This flag's status is cleared when this bit is read, unless this bit is set again on account of another

power-on-reset event in the intervening period.

OFLO_FLAGS:

OFLO_FLAGS is used to indicate whether the modulator is over-ranged or under-ranged. The following

conditions are possible:

1. OFLO_FLAGS = 0x0: Normal Operation

2. OFLO_FLAGS = 0x1: The differential input is more than (±VREF/Gain) but is not more than

±(1.3*VREF/Gain) to cause a modulator over-range.

3. OFLO_FLAGS = 0x2: The modulator was over-ranged towards +VREF/Gain.

4. OFLO_FLAGS = 0x3: The modulator was over-ranged towards −VREF/Gain.

The condition of OFLO_FLAGS = 10b or 11b can be used in conjunction with the RAILS_FLAG to determine the

fault condition.

SAMPLED_CH:

These three bits show the channel number for which the ADC_DOUT and SENDIAG_FLAGS are available. This

does not necessarily indicate the current channel under conversion because the conversion frame and

computation of results from the channels are pipelined. That is, while the conversion is going on for a particular

channel, the results for the previous conversion (of the same or a different channel) are available.

SERIAL DIGITAL INTERFACE

A synchronous 4-wire serial peripheral interface (SPI) provides access to the internal registers of LMP90xxx via

CSB, SCLK, SDI, SDO/DRDYB.

All registers are memory-mapped. A register address (ADDR) is composed of an upper register address (URA)

and lower register address (LRA) as shown in Table 6. For example, ADDR 0x3A has URA=0x3 and LRA=0xA.

Table 6. ADDR Map

Bit [6:4] [3:0]

Name URA LRA

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