Datasheet

CSB
SCLK
0.7V
IO
t
CSHmin
CSB
SCLK
0.3V
IO
0.7V
IO
t
CSSUmin
CSB
SCLK
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
n
LSB
INST2
SDI
MSB
SDO/
DRDYB
Data Byte (s)
DRDYB is driving the pin
SDO is driving the pin
LSB
1/f
SCLK
t
CL
t
CH
LMP90100
www.ti.com SNAS510P –JANUARY 2011–REVISED MARCH 2013
Timing Diagrams
Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
; the
typical values apply for T
A
= +25°C.
Figure 3. Timing Diagram
Symbol Parameter Conditions Min Typical Max Units
f
SCLK
10 MHz
t
CH
SCLK High time 0.4 / f
SCLK
ns
t
CL
SCLK Low time 0.4 / f
SCLK
ns
Symbol Parameter Conditions Min Typical Max Units
CSB Setup time prior to an SCLK
t
CSSU
5 ns
rising edge
CSB Hold time after the last rising
t
CSH
6 ns
edge of SCLK
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