Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 24 Bit HTSSOP 28

LMP90100

www.ti.com

SNAS510P –JANUARY 2011–REVISED MARCH 2013

LMP90100/LMP90099/LMP90098/LMP90097 Sensor AFE System: Multi-Channel, Low

Power 24-Bit Sensor AFE with True Continuous Background Calibration

Check for Samples: LMP90100

FEATURES

APPLICATIONS

• 24-Bit Low Power Sigma Delta ADC

• Temperature and Pressure Transmitters

• True Continuous Background Calibration at all • Strain Gauge Interface

gains

• Industrial Process Control

• In-Place System Calibration using Expected

Value programming DESCRIPTION

The LMP90100/LMP90099/LMP90098/LMP90097 are

• Low-Noise programmable gain (1x - 128x)

highly integrated, multi-channel, low power 24-bit

• Continuous background open/short and out of

Sensor AFEs. The devices features a precision, 24-

range sensor diagnostics

bit Sigma Delta Analog-to-Digital Converter (ADC)

• 8 output data rates (ODR) with single-cycle

with a low-noise programmable gain amplifier and a

settling

fully differential high impedance analog input

multiplexer. A true continuous background calibration

• 2 matched excitation current sources from 100

feature allows calibration at all gains and output data

µA to 1000 µA (LMP90100/LMP90098)

rates without interrupting the signal path. The

• 4-DIFF / 7-SE inputs (LMP90100/LMP90099)

background calibration feature essentially eliminates

• 2-DIFF / 4-SE inputs (LMP90098/LMP90097)

gain and offset errors across temperature and time,

providing measurement accuracy without sacrificing

• 7 General Purpose Input/Output pins

speed and power consumption.

• Chopper-stabilized buffer for low offset

Another feature of the

• SPI 4/3-wire with CRC data link error detection

LMP90100/LMP90099/LMP90098/LMP90097 is

• 50 Hz to 60 Hz line rejection at ODR ≤13.42

continuous background sensor diagnostics, allowing

SPS

the detection of open and short circuit conditions and

• Independent gain and ODR selection per out-of-range signals, without requiring user

intervention, resulting in enhanced system reliability.

channel

• Supported by Webench Sensor AFE Designer

Two sets of independent external reference voltage

pins allow multiple ratiometric measurements. In

• Automatic Channel Sequencer

addition, two matched programmable current sources

are available in the LMP90100/LMP90098 to excite

KEY SPECIFICATIONS

external sensors such as resistive temperature

• ENOB/NFR Up to 21.5/19 bits

detectors and bridge sensors. Furthermore, seven

GPIO pins are provided for interfacing to external

• Offset Error (typ) 8.4 nV

LEDs and switches to simplify control across an

• Gain Error (typ) 7 ppm

isolation barrier.

• Total Noise < 10 µV-rms

Collectively, these features make the

• Integral Non-Linearity (INL max) ±15 ppm of

LMP90100/LMP90099/LMP90098/LMP90097

FSR

complete analog front-ends for low power, precision

• Output Data Rates (ODR) 1.6775 - 214.65 SPS

sensor applications such as temperature, pressure,

strain gauge, and industrial process control. The

• Analog Voltage, VA +2.85 to +5.5 V

LMP90100/LMP90099/LMP90098/LMP90097 are

• Operating Temp Range -40°C to 125 °C

ensured over the extended temperature range of -

• Package 28 Pin HTSSOP exposed pad

40°C to +125°C and are available in a 28-pin

HTSSOP package with an exposed pad.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of National Semiconductor Corporation.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (69 pages)

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LMP90100 www.ti.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Application 2 -Wire RTD 3-Wire RTD IB1 2 3 4 SCLK IB2 VIN0 ... VIN2 ... VIN4 ... VIN6/VREFP2 VIN7/ VREFN2 2 VIO CSB 1 + VREFP1 VREFN1 VA 4-Wire RTD Thermocouple VA GND SDO/DRDYB LMP90100 LM90xxx 24-bit Sensor AFE Family of Products MicroController SDI D0 ...
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Block Diagram Chip Configurable LMP90xxx Channel Configurable Fixed EXC. CURRENT EXC. CURRENT IB1 LMP90100/LMP9 0098 only VIO VA VA IB2 POR Open/Short Sensor Diag. VIN0 VIN1 VIN3 LMP90100/LMP9 0099 only VIN4 VIN5 BACKGROUND CALIBRATION INPUT MUX VIN2 FGA 16x PGA 1x, 2x, 4x, 8x SERIAL I/F CONTROL & CALIBRATION DATA PATH SCLK SDI SDO/DRDYB CSB BUFF 24 bit SD Module VIN6/VREFP2 DIGITAL FILTER VIN7/VREFN2 CLK MUX VREF Ext.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com • True Continuous Background Calibration The LMP90100/LMP90099/LMP90098/LMP90097 feature a 24 bit ΣΔ core with continuous background calibration to compensate for gain and offset errors in the ADC, virtually eliminating any drift with time and temperature.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Connection Diagram LMP90100/ LMP90099 only VA 1 28 VIO VIN0 2 27 D6/DRDYB VIN1 3 26 D5 VIN2 4 25 D4 VIN3 5 24 D3 VIN4 6 23 D2 22 D1 VIN5 7 VREFP1 8 VREFN1 LMP90xxx 28-pin HTSSOP 21 D0 9 20 SDO/DRDYB SDI VIN6/VREFP2 10 19 VIN7/VREFN2 11 18 SCLK IB2 12 17 CSB IB1 13 16 GND XOUT 14 15 XIN/CLK LMP90100/ LMP90098 only Figure 2.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Analog Supply Voltage, VA -0.3V to 6.0V Digital I/O Supply Voltage, VIO -0.3V to 6.0V Reference Voltage, VREF -0.3V to VA+0.3V Voltage on Any Analog Input Pin to GND (3) -0.3V to VA+0.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol n Parameter Conditions Min Typ Resolution ENOB / NFR ODR INL Effective Number of Bits and Noise Free Resolution 3V / all / ON / OFF / all. Shorted input. Table 1 Bits 5V / all / ON / OFF / all.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Electrical Characteristics (continued) Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol NMRR Parameter Normal Mode Rejection Ratio (2) Cross-talk Conditions Min 47 Hz to 63 Hz, 5V / 13.42 / OFF / OFF /1 Typ Max Units 78 3V / 214.65 / OFF / OFF / 1 95 136 dB 5V / 214.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol Parameter Differential Input Impedance ZIN Conditions Min ODR = 13.42 SPS Typ Max Units 15.4 MOhm CINP Capacitance of the 5V / 214.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Electrical Characteristics (continued) Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol IBMT IBMTC Parameter Conditions IB1/IB2 Matching IB1/IB2 Matching Drfit Typ Max Units 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 100 µA Min 0.34 1.53 % 3V & 5V / 214.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Table 2. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V Gain ODR (SPS) 1 2 4 8 16 32 64 128 1.6775 20.5 (18) 20.5 (18) 19.5 (17) 19 (16.5) 20.5 (18) 19.5 (17) 19 (16.5) 18 (15.5) 3.355 20 (17.5) 20 (17.5) 19 (16.5) 18.5 (16) 20 (17.5) 19 (16.5) 18.5 (16) 17 (14.5) 6.71 19.5 (17) 19.5 (17) 18.5 (16) 18 (15.5) 19.5 (17) 18.5 (16) 17.5 (15) 17 (14.5) 13.42 19 (16.5) 18.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Timing Diagrams Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. CSB tCH SCLK 1 2 3 1/fSCLK tCL 4 5 6 7 8 9 10 11 12 13 14 15 16 n 17 INST2 SDI MSB LSB DRDYB is driving the pin SDO is driving the pin Data Byte (s) SDO/ DRDYB MSB LSB Figure 3.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com 0.9VIO 0.9VIO 0.7VIO SCLK SCLK 0.1VIO 0.1VIO t CLKR t DISU t CLKF 0.7VIO DB 0.3VIO 0.3VIO 0.7VIO SDI Symbol Parameter t DIH Conditions Min Typical Max Units tCLKR SCLK Rise time 1.15 ns tCLKF SCLK Fall time 1.15 ns tDISU SDI Setup time prior to an SCLK rising edge 5 ns tDIH SDI Hold time after an SCLK rising edge 6 ns 0.7VIO SCLK 0.3VIO CSB t DOH t DOD1 t DOA 0.9VIO 0.7VIO 0.7VIO 0.3VIO 0.
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LMP90100 www.ti.com SCLK SNAS510P – JANUARY 2011 – REVISED MARCH 2013 8 0.9VIO 0.9VIO 9 0.3VIO SDO tDOE 0.1VIO 0.7VIO SDO 0.1VIO t DOR t DOF DB7 0.3VIO Symbol Parameter Conditions Min Typical Max Units 35 ns tDOE SDO Enable time from the falling edge of the 8th SCLK tDOR SDO Rise time (1) 7 tDOF SDO Fall time (1) 7 ns ODR ≤ 13.42 SPS 64 µs 13.42 < ODR ≤ 214.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com PSRR = 20 LOG (ΔVA / ΔOutput Offset) Typical Performance Characteristics Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C. ENOB vs. Gain without Calibration at ODR = 13.42 SPS ENOB vs. Gain with Calibration at ODR = 13.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C. Noise vs. Gain without Calibration at ODR = 214.65 SPS Noise vs. Gain with Calibration at ODR = 214.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C. Gain Error vs. Temperature without Calibration at Gain = 1 Gain Error vs.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C. INL at Gain = 1 INL (ppm of FSR) 10 5 0 -5 VA = 5V, 13.4 SPS -10 -5 -4 -3 -2 -1 0 1 VIN (V) 2 3 4 5 Figure 34.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION Throughout this datasheet, the LMP90100/LMP90099/LMP90098/LMP90097 will be referred to as the LMP90xxx. The LMP90xxx is a low-power 24-Bit ΣΔ ADC with 4 fully differential / 7 single-ended analog channels for the LMP90100/LMP90099 and 2 full differential / 4 single-ended for the LMP90098/LMP90097. Its serial data output is two’s complement format. The output data rate (ODR) ranges from 1.6775 SPS to 214.65 SPS.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 VREFP1 VIN0 VIN1 VIN2 VIN3* VINP + + - ADC BUFF FGA VINN + - - VIN4* VIN5* VIN6/VREFP2 VIN7/VREFN2 VREFN1 * VIN3, VIN4, VIN5 are only available for LMP90100 and LMP90099 Figure 35. Simplified VIN Circuitry Selectable Gains (FGA & PGA) LMP90xxx provides two types of gain amplifiers: a fixed gain amplifier (FGA) and a programmable gain amplifier (PGA).
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Note that these ODRs are meant for a single channel conversion; the ODR needs to be divided by n for n channels scanning. For example, if the ADC were running at 214.65 SPS and four channels are being scanned, then the ODR per channel would be 214.65/4 = 53.6625 SPS. Digital Filter The LMP90xxx has a fourth order rotated sinc filter that is used to configure various ODRs and to reject power supply frequencies of 50Hz and 60Hz.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 -60 www.ti.com 13.42 SPS -70 GAIN (dB) -80 -90 -100 -110 -120 45 47 49 51 53 55 57 59 61 63 65 1800 2000 FREQUENCY (Hz) Figure 39. Digital Filter Response at 13.42 SPS 0 26.83125 SPS 53.6625 SPS GAIN (dB) -40 -80 -120 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY (Hz) Figure 40. Digital Filter Response, 26.83125 SPS and 53.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 0 107.325 SPS 214.65 SPS GAIN (dB) -40 -80 -120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (Hz) Figure 41. Digital Filter Response 107.325 SPS and 214.65 SPS If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the filter response would be the same as the response shown above, but the frequency will change according to the equation: fNEW = [(CLKEXT) / 256 ] x (fOLD / 13.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com inputs outputs Pins D0 ± D6 = Set GPIO_DIRCNx = 0 Set GPIO_DIRCNx = 1 Read the GPIO_DAT: Dx bit to determine if Dx is high or low, where 0 ” [ ” 6. Write to GPIO_DAT: Dx bit to drive Dx high or low, where 0 ” [ ” 6. Figure 43. GPIO Register Settings CALIBRATION As seen in Figure 44, there are two types of calibration: background calibration and system calibration. These calibrations are further described in the next sections.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 The benefits of using type 2 calibration is a higher throughput, lower power consumption, and slightly better noise. The exact savings would depend on the number of channels being scanned, and the ODR and gain of each channel. Using Background Calibration: There are four modes of background calibration, which can be programmed using the BGCALCN bits. They are as follows: 1. BgcalMode0: Background Calibration OFF 2.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com A data-flow diagram of these coefficients can be seen in Figure 46. Uncalibrated VIN ± OFFSET [CHx_SCAL_ OFFSET] y Calibrated ADC_DOUT GAIN [CHx_SCAL_ GAIN] Figure 46. System Calibration Data-Flow Diagram There are four distinct sets of System Calibration Offset and System Calibration Gain Registers for use with CH0-CH3. CH4-CH6 reuse the registers of CH0-CH2, respectively.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 4. Enter the System Calibration Gain Coefficient Determination mode by programming 0x3 in the SCALCN register. 5. LMP90xxx starts a fresh conversion at the selected output data rate for the channel. At the end of the conversion, the CHx_SCAL_GAIN is filled-in (or overwritten) with the System Calibration Gain coefficient. 6. The System Calibration Gain Coefficient Determination mode is automatically exited. 7.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com ScanMode1: Multiple-Channels Single Scan LMP90xxx converts one or more channels starting from FIRST_CH to LAST_CH, and then enters the stand-by state. ScanMode2: Multiple-Channels Continuous Scan LMP90xxx continuously converts one or more channels starting from FIRST_CH to LAST_CH, and then it repeats this process.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Burnout Current = 10 PA VIN0 VIN1 VIN2 VIN3* VINP VINN VIN4* VIN5* VIN6/VREFP2 VIN7/VREFN2 Burnout Current = 10 PA * VIN3, VIN4, VIN5 are only available for LMP90100 and LMP90099 Figure 48. Burnout Currents Burnout Current Injection: Burnout currents are injected differently depending on the channel scan mode selected.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Burnout Currents BURNOUT_EN CH0 is being sampled CH0 CH1 CH2 CH3 BURNOUT_EN CH1 is being sampled CH0 CH1 CH2 CH3 BURNOUT_EN CH2 is being sampled CH0 CH1 CH2 CH3 BURNOUT_EN CH3 is being sampled CH0 CH1 CH2 CH3 Figure 49. Burnout Currents Injection for ScanMode3 Sensor Diagnostic Flags Burnout currents can be used to verify that an external sensor is still operational before attempting to make measurements on that channel.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 SHORT_THLD_FLAG: The short circuit threshold flag is used to report a short-circuit condition. It is set when the output voltage (VOUT) is within the absolute Vthreshold. Vthreshold can be programmed using the 8-bit SENDIAG_THLDH register concatenated with the 8-bit SENDIAG_THLDL register. For example, assume VREF = 5V, gain = 1, SENDIAG_THLDH = 0xFA, and SENDIAG_THLDL = 0x45.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Register Read/Write Protocol Figure 51 shows the protocol how to write to or read from a register. Transaction 1 sets up the upper register address (URA) where the user wants to start the register-write or register-read. Transaction 2 sets the lower register address (LRA) and includes the Data Byte(s), which contains the incoming data from the master or outgoing data from the LMP90xxx.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 If streaming reaches ADDR 0x7F, then it will wrap back to ADDR 0x00. Furthermore, reading back the Upper Register Address after streaming will report the Upper Register Address at the start of streaming, not the Upper Register Address at the end of streaming. To stream, write 0x3 to INST2’s SZ bits as seen in Figure 51. To select the stream type, program the SPI_STREAMCN: STRM_TYPE bit.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com 1/ODR D6 = drdyb 1/ODR ADC Data 1 ADC Data 2 Valid ADC_DOUT (ADC Data 2) Valid ADC_DOUT (ADC Data 1) LSB MSB SDO MSB LSB Figure 54. DRDYB Behavior for an Incomplete ADC_DOUT Reading DRDYB can also be accessed via registers using the DT_AVAIL_B bit. This bit indicates when fresh conversion data is available in the ADC_DOUT registers. If new conversion data is available, then DT_AVAIL_B = 0; otherwise, DT_AVAIL_B = 1.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 CSB tCH SCLK 1 2 3 1/fSCLK tCL 4 5 6 7 8 9 10 11 12 13 14 15 16 n 17 INST2 SDI MSB LSB DRDYB is driving the pin SDO is driving the pin Data Byte (s) SDO/ DRDYB MSB LSB Figure 56. Timing Protocol for DrdybCase1 DrdybCase2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03 SDO/DRDYB can be made independent of CSB by setting SDO_DRDYB_DRIVER = 0x03 in the SPI Handshake Control register.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com DrdybCase3: Routing DRDYB to D6 LMP90100 uC SCLK SCLK CSB CSB SDI MOSI SDO MISO Interrupt D6 = DRDYB Figure 58. DrdybCase3 Connection Diagram The drdyb signal can be routed to pin D6 by setting SPI_DRDYB_D6 high and SDO_DRDYB_DRIVER to 0x4. This is the behavior for DrdybCase3 as shown in Figure 58. The timing protocol for this case can be seen in Figure 59.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Table 7.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com 1/ODR CH0 1/ODR CH1 SDO LSB MSB MSB LSB Reading SPI_CRC_DAT Reading ADC_DOUT of CH1 Reading SPI_CRC_DAT Reading ADC_DOUT of CH0 LSB MSB MSB LSB Figure 61. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds Follow the steps below to enable CRC: 1. Set SPI_CRC_CN = 1 (register 0x13, bit 4) to enable CRC. 2. Set DRDYB_AFT_CRC = 1 (register 0x13, bit 2) to dessert the DRDYB after CRC. 3.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 If it is desirable to reset the System Calibration Coefficient Registers, then set RESET_SYSCAL = 1 before writing 0xC3 to REG_AND_CNV_RST. If the device is operating in the “System Calibration Offset/Gain Coefficient Determination” mode (SCALCN register), then write REG_AND_CNV_RST = 0xC3 twice to get out of this mode. After a register reset, any on-going conversions will be aborted and restarted.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION QUICK START This section shows step-by-step instructions to configure the LMP90xxx to perform a simple DC reading from CH0. 1. Apply VA = VIO = VREFP1 = 5V, and ground VREFN1 2. Apply VINP = ¾VREF and VINN = ¼VREF for CH0. Thus, set CH0 = VIN = VINP - VINN = ½VREF (CH0_INPUTCN register) 3. Set gain = 1 (CH0_CONFIG: GAIN_SEL = 0x0) 4. Exclude the buffer from the signal path (CH0_CONFIG: BUF_EN = 1) 5.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 ADC_DOUT 8,388,607d -1 LSB | | (-VREF + 1LSB) 1d | | +1LSB - 16, 777, 215d VIN (VREF - 1LSB) | | - 8,388,608d Figure 63. ADC_DOUT vs. VIN of a 24-Bit Resolution (VREF = 5.5V, Gain = 1). REGISTER READ/WRITE EXAMPLES Writing to Register Examples Using the register read/write protocol shown in Figure 51, the following example shows how to write three data bytes starting at register address (ADDR) 0x1F.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Transaction 2 ± Data Access Instruction Byte 2 (INST2) Data Byte (s) 7 [6:5] 4 [3:0] [7:0] 0 0x00 0 0x2 One Data Byte will be written to ADDR 0x12. After this process, deassert CSB. R/WB = Read/Write Data 0: Write Data 1: Read Data SZ = Size 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: Streaming ± 3+ bytes until CSB is de-asserted Figure 65.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 STREAMING EXAMPLES Normal Streaming Example This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode. Because the default STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can be omitted. Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA. Instruction Byte 1 (INST1) Upper Address Byte (UAB) [7:0] [7:3] [2:0] 0x10 0x0 0x1 R/WB = Read/Write Address 0x10: Write Address 0x90: Read Address Transaction 2 ± Data Access Instruction Byte 2 (INST2) Data Byte (s) 7 [6:5] 4 [3:0] [95:0] 1 0x3 0 0xA Read ADC_DOUTH, ADC_DOUTM, and ADC_DOUTL four times.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 + 1 PF www.ti.com 3V 3V VA VIO + 0.1 PF 0.1 PF 1 PF SCLK IB1 CSB IB1 = 1 mA SDO SDI drdyb = D6 VIN0 LMP90100 RLINE1 RTD PT-100 RCOMP = 0: D5 VIN1 RLINE2 Microcontroller IB2 = 1 mA IB2 12 pF VIN6/VREFP2 RLINE3 3.57 MHz XOUT RREF VIN7/VREFN2 XIN/CLK 12 pF Figure 70. Topology #1: 3-wire RTD Using 2 Current Sources Figure 70 shows the first topology for a 3-wire resistive temperature detector (RTD) application.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 3V 3V + + 0.1 PF 2.2 PF 0.1 PF VA 1 PF VIO SCLK IB1 IB1 = 1 mA CSB SDO/DRDYB RLINE1 SDI VIN0 Microcontroller RTD PT-100 LMP90100 D2 VIN1 RLINE2 VIN6/VREFP2 RLINE3 RREF OSC XIN/CLK VIN7/VREFN2 51: Figure 71. Topology #2: 3-wire RTD Using 1 Current Source Figure 71 shows the second topology for a 3-wire RTD application. Topology #2 shows the same connection as topology #1, but without IB2.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Thermocouple and IC Analog Temperature 5V 2.7V VA VIO + + 0.1 PF 1 PF Thermocouple 10 nF VREFP1 SCLK + TC [ VIN4 ± VIN3] - 2.2 PF CSB SDO 2k SDI VIN3 2k 1 PF Tcold VIN4 Thot 0.1 PF D6 = DRDYB 10 nF LMP90100 Microcontroller 5V LM94022 IC Temp Sensor + 1 PF Tcold VIN5 + LM [ VIN5] - 0.1 PF XOUT VIN7 5V VREFP1 LM4140-4.1 + 1 PF 0.1 PF 0.1 PF XIN/CLK VREFN1 GND Figure 72.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 REGISTERS 1. If written to, RESERVED bits must be written to only 0 unless otherwise indicated. 2. Read back value of RESERVED bits and registers is unspecified and should be discarded. 3. Recommended values must be programmed and forbidden values must not be programmed where they are indicated in order to avoid unexpected results. 4. If written to, registers indicated as Reserved must have the indicated default value as shown below.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Table 10. PWRCN: Power Mode Control and Status (Address 0x08) Bit Bit Symbol Bit Description [7:2] Reserved Power Control Write Only – power down mode control 0x0: Active Mode 0x1: Power-down Mode 0x3: Stand-by Mode [1:0] PWRCN Read Only – the present mode is: 0x0 (default): Active Mode 0x1: Power-down Mode 0x3: Stand-by Mode ADC REGISTERS Table 11.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Table 13. ADC_DONE: ADC Data Available (Address 0x18) Bit Bit Symbol Bit Description Data Available – indicates if new conversion data is available 0x00 − 0xFE: Available 0xFF: Not available [7:0] DT_AVAIL_B Table 14.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Table 16. CH_SCAN: Channel Scan Mode (Address 0x1F) (continued) Bit Bit Symbol Bit Description Starting channel for conversion 0x0 (default): CH0 0x1: CH1 0x2: CH2 FIRST_CH 0x3: CH3 [2:0] (CH4 to CH6 for LMP90100 and 0x4: CH4 LMP90099 only) 0x5: CH5 0x6: CH6 Note: FIRST_CH cannot be greater than LAST_CH. For example, if FIRST_CH = CH1, then LAST_CH cannot be CH0. If 0x7 is written it is ignored.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Table 18. Default VINx for CH0-CH6 VINP VINN CH0 VIN0 VIN1 CH1 VIN2 VIN3 (LMP90100/LMP90099 only) CH2 VIN4 (LMP90100/LMP90099 only) VIN5 (LMP90100/LMP90099 only) CH3 VIN6 VIN7 CH4 (LMP90100/LMP90099 only) VIN0 VIN1 CH5 (LMP90100/LMP90099 only) VIN2 VIN3 CH6 (LMP90100/LMP90099 only) VIN4 VIN5 Table 19.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Table 21.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Table 27. SENDIAG_FLAGS: Sensor Diagnostic Flags (Address 0x19) Bit Bit Symbol Bit Description 7 SHORT_THLD_ FLAG Short Circuit Threshold Flag = 1 when the absolute value of VOUT is within the absolute threshold voltage set by SENDIAG_THLDH and SENDIAG_THLDL. 6 RAILS_FLAG Rails Flag = 1 when at least one of the inputs is near rail (VA or GND).
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Table 31. DATA_ONLY_2: Data Only Read Control 2 (Address 0x0A) Bit [7:3] Bit Symbol Bit Description Reserved - DATA_ONLY_SZ Number of bytes to be read out in Data Only mode. A value of 0x0 means read one byte and 0x7 means read 8 bytes. Default: 0x2 [2:0] Table 32.
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LMP90100 SNAS510P – JANUARY 2011 – REVISED MARCH 2013 www.ti.com Table 35. GPIO_DIRCN: GPIO Direction (Address 0x0E) (continued) Bit x Bit Symbol Bit Description GPIO direction control – these bits are used to control the direction of each General Purpose Input/Outputs (GPIO) pins D0 - D6. 0 (default): Dx is an Input 1: Dx is an Output where 0 ≤ x ≤ 6. GPIO_DIRCNx For example, writing a 1 to bit 6 means D6 is an Output. Note: If D6 is used for DRDYB, then it cannot be used for GPIO. Table 36.
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LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision O (March 2013) to Revision P • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMP90097MHE/NOPB HTSSOP PWP 28 250 178.0 16.4 LMP90097MHX/NOPB HTSSOP PWP 28 2500 330.0 LMP90098MHE/NOPB HTSSOP PWP 28 250 178.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP90097MHE/NOPB HTSSOP PWP LMP90097MHX/NOPB HTSSOP PWP 28 250 213.0 191.0 55.0 28 2500 367.0 367.0 38.0 LMP90098MHE/NOPB HTSSOP PWP LMP90098MHX/NOPB HTSSOP PWP 28 250 213.0 191.0 55.0 28 2500 367.0 367.0 LMP90099MHE/NOPB HTSSOP 38.0 PWP 28 250 213.0 191.0 55.
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MECHANICAL DATA PWP0028A MXA28A (Rev D) www.ti.
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