Datasheet
Table Of Contents
- FEATURES
- Key Specifications
- Applications
- DESCRIPTION
- Absolute Maximum Ratings
- Operating Ratings
- Electrical Characteristics
- Specific Definitions
- Typical Performance Characteristics
- Functional Description
- Applications Information
- Revision History
LMP90077, LMP90078, LMP90079, LMP90080
SNAS521F –JULY 2011–REVISED MARCH 2013
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Table 21. SCALCN
System Calibration Control (Address 0x17)
Bit Bit Symbol Bit Description
[7:2] Reserved -
System Calibration Control
When written, set SCALCN to:
0x0 (default): Normal Mode
0x1: “System Calibration Offset Coefficient Determination” mode
0x2: “System Calibration Gain Coefficient Determination” mode
[1:0] SCALCN 0x3: Reserved
When read, this bit indicates the system calibration mode is in:
0x0: Normal Mode
0x1: "System Calibration Offset Coefficient Determination" mode
0x2: "System Calibration Gain Coefficient Determination" mode
0x3: Reserved
(1)
(1) When read, this bit will indicate the current System Calibration status. Since this coefficient determination mode will only take 1
conversion cycle, reading this register will only return 0x00, unless this register is read within 1 conversion window.
Table 22. CHx_SCAL_OFFSET
CH0-CH3 System Calibration Offset Registers (Two's-Complement)
ADDR
Name Description
CH0 CH1 CH2 CH3
0x30 0x38 0x40 0x48 CHx_SCAL_OFFSETH System Calibration Offset Coefficient Data [15:8]
0x31 0x39 0x41 0x49 CHx_SCAL_OFFSETM System Calibration Offset Coefficient Data [7:0]
0x32 0x3A 0x42 0x4A Reserved -
Table 23. CHx_SCAL_GAIN
CH0-CH3 System Calibration Gain Registers (Fixed Point 1.23 Format)
ADDR
Name Description
CH0 CH1 CH2 CH3
0x33 0x3B 0x43 0x4B CHx_SCAL_GAINH System Calibration Gain Coefficient Data [15:8]
0x34 0x3C 0x44 0x4C CHx_SCAL_GAINL System Calibration Gain Coefficient Data [7:0]
0x35 0x3D 0x45 0x4D Reserved -
Table 24. CHx_SCAL_SCALING
CH0-CH3 System Calibration Scaling Coefficient Registers
ADDR
Name Description
CH0 CH1 CH2 CH3
0x36 0x3E 0x46 0x4E CHx_SCAL_SCALING System Calibration Scaling Coefficient Data [5:0]
Table 25. CHx_SCAL_BITS_SELECTOR
CH0-CH3 System Calibration Bit Selector Registers
ADDR
Name Description
CH0 CH1 CH2 CH3
0x37 0x3F 0x47 0x4F CHx_SCAL_BITS_SELECTOR System Calibration Bit Selection Data [2:0]
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