Datasheet

LMP90077, LMP90078, LMP90079, LMP90080
SNAS521F –JULY 2011–REVISED MARCH 2013 www.ti.com
Table 10. PWRCN
Power Mode Control and Status (Address 0x08)
Bit Bit Symbol Bit Description
[7:2] Reserved -
Power Control
Write Only – power down mode control
0x0: Active Mode
0x1: Power-down Mode
0x3: Stand-by Mode
[1:0] PWRCN
Read Only – the present mode is:
0x0 (default): Active Mode
0x1: Power-down Mode
0x3: Stand-by Mode
ADC REGISTERS
Table 11. ADC_RESTART
ADC Restart Conversion (Address 0x0B)
Bit Bit Symbol Bit Description
[7:1] Reserved -
Restart conversion
0 RESTART
1: Restart conversion.
Table 12. ADC_AUXCN
ADC Auxiliary Control (Address 0x12)
Bit Bit Symbol Bit Description
7 Reserved -
The System Calibration registers (CHx_SCAL_OFFSET and CHx_SCAL_GAIN) are:
6 RESET_SYSCAL 0 (default): preserved even when "REG_AND_CNV_ RST" = 0xC3.
1: reset by setting "REG_AND_CNV_ RST" = 0xC3.
External clock detection
5 CLK_EXT_DET 0 (default): "External Clock Detection" is operational
1: "External-Clock Detection" is bypassed
Clock select – only valid if CLK_EXT_DET = 1
4 CLK_SEL 0 (default): Selects internal clock
1: Selects external clock
Selects RTD Current as follows:
0x0 (default): 0 µA
0x1: 100 µA
0x2: 200 µA
0x3: 300 µA
0x4: 400 µA
RTD_CUR_SEL (LMP90080
[3:0]
and LMP90078 only)
0x5: 500 µA
0x6: 600 µA
0x7: 700 µA
0x8: 800 µA
0x9: 900 µA
0xA: 1000 µA
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