Datasheet

LMP90077, LMP90078, LMP90079, LMP90080
www.ti.com SNAS521F –JULY 2011–REVISED MARCH 2013
Table 7. REGISTER MAP (continued)
Register Name ADDR (URA & LRA) Type Default
CH6_CONFIG CH6 Configuration 0x2D R/W 0x70
Reserved - 0x2E - 0x2F - 0x00
SYSTEM CALIBRATION REGISTERS
CH0_SCAL_OFFSET CH0 System Calibration Offset Coefficients 0x30 - 0x31 R/W 0x0000
Reserved - 0x32 - 0x00
CH0_SCAL_GAIN CH0 System Calibration Gain Coefficients 0x33 - 0x34 R/W 0x8000
Reserved - 0x35 - 0x00
CH0_SCAL_SCALING CH0 System Calibration Scaling Coefficients 0x36 R/W 0x01
CH0_SCAL_BITS_
CH0 System Calibration Bit Selector 0x37 R/W 0x00
SELECTOR
CH1_SCAL_OFFSET CH1 System Calibration Offset Coefficients 0x38 - 0x39 R/W 0x0000
Reserved - 0x3A - 0x00
CH1_SCAL_GAIN CH1 System Calibration Gain Coefficient 0x3B - 0x3C R/W 0x8000
Reserved - 0x3D - 0x00
CH1_SCAL_SCALING CH1 System Calibration Scaling Coefficients 0x3E R/W 0x01
CH1_SCAL_BITS_SELECT
CH1 System Calibration Bit Selector
OR 0x3F R/W 0x00
CH2_SCAL_OFFSET CH2 System Calibration Offset Coefficients 0x40 - 0x41 R/W 0x0000
Reserved - 0x42 - 0x00
CH2_SCAL_GAIN CH2 System Calibration Gain Coefficient 0x43 - 0x44 R/W 0x8000
Reserved - 0x45 - 0x00
CH2_SCAL_SCALING CH2 System Calibration Scaling Coefficients 0x46 R/W 0x01
CH2_SCAL_BITS_
CH2 System Calibration Bit Selector 0x47 R/W 0x00
SELECTOR
CH3_SCAL_OFFSET CH3 System Calibration Offset Coefficients 0x48 - 0x49 R/W 0x0000
Reserved - 0x4A - 0x00
CH3_SCAL_GAIN CH3 System Calibration Gain Coefficient 0x4B - 0x4C R/W 0x8000
Reserved - 0x4D - 0x00
CH3_SCAL_SCALING CH3 System Calibration Scaling Coefficients 0x4E R/W 0x01
CH3_SCAL_BITS_
CH3 System Calibration Bit Selector 0x4F R/W 0x00
SELECTOR
Reserved - 0x50 - 0x7F - 0x00
POWER AND RESET REGISTERS
Table 8. RESETCN
Reset Control (Address 0x00)
Bit Bit Symbol Bit Description
Register and Conversion Reset0xC3: Register and conversion reset
[7:0] REG_AND_CNV_ RST
Others: Neglected
Table 9. SPI_RESET
SPI Reset Control (Address 0x02)
Bit Bit Symbol Bit Description
SPI Reset Enable
[0] SPI_ RST 0x0 (default): SPI Reset Disabled
0x1: SPI Reset Enabled
(1)
(1) Once written, the contents of this register are sticky. That is, the content of this register cannot be changed with subsequent write.
However, a Register reset clears the register as well as the sticky status.
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