Datasheet

CSB
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n
INST2
SDI
MSB
LSB
Drdyb = D6
SDO
Data Byte (s)
High-Z
MSB
LSB
...
LMP90077, LMP90078, LMP90079, LMP90080
www.ti.com SNAS521F –JULY 2011–REVISED MARCH 2013
Figure 54. Timing Protocol for DrdybCase3
Data Only Read Transaction
In a data only read transaction, one can directly access the data byte(s) as soon as the CSB is asserted without
having to send any instruction byte. This is useful as it brings down the latency as well as the overhead
associated with the instruction byte (as well as the Upper Address Byte, if any).
In order to use the data only transaction, the device must be placed in the data first mode. The following table
lists transaction formats for placing the device in and out of the data first mode and reading the mode status.
Table 6. Data First Mode Transactions
Bit[7] Bits[6:5] Bit[4] Bits[3:0] Data Bytes
Enable Data First Mode Instruction 1 11 1 1010 None
Disable Data First Mode Instruction 1 11 1 1011 None
Read Mode Status Transaction 1 00 1 1111 One
Note that while being in the data first mode, once the data bytes in the data only read transaction are sent out,
the device is ready to start on any normal (non-data-only) transaction including the Disable Data First Mode
Instruction. The current status of the data first mode (enabled/disabled status) can be read back using the Read
Mode Status Transaction. This transaction consists of the Read Mode Status Instruction followed by a single
data byte (driven by the device). The data first mode status is available on bit [1] of this data byte.
The data only read transaction allows reading up to eight consecutive registers, starting from any start address.
Usually, the start address will be the address of the most significant byte of conversion data, but it could just as
well be any other address. The start address and number of bytes to be read during the data only read
transaction can be programmed using the DATA_ONLY_1 AND DATA_ONLY_2 registers respectively.
The upper register address is unaffected by a data only read transaction. That is, it retains its setting even after
encountering a data only transaction. The data only transaction uses its own address (including the upper
address) from the DATA_ONLY_1 register. When in the data first mode, the SCLK must stop high before
entering the Data Only Read Transaction; this transaction should be completed before the next scheduled
DRDYB deassertion.
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