Datasheet

CSB
SCLK
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
n
LSB
INST2
SDI
MSB
SDO/
DRDYB
Data Byte (s)
DRDYB is driving the pin
SDO is driving the pin
LSB
1/f
SCLK
t
CL
t
CH
...
LMP900xx
SCLK
CSB
SDI
SDO/
DRDYB
uC
SCLK
CSB
MOSI
MISO
INT
LMP90077, LMP90078, LMP90079, LMP90080
www.ti.com SNAS521F –JULY 2011–REVISED MARCH 2013
DrdybCase1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00
Figure 50. DrdybCase1 Connection Diagram
As shown in Figure 50, the drdyb signal and SDO can be multiplexed on the same pin as their functions are
mostly complementary. In fact, this is the default mode for the SDO/DRDYB pin.
Figure 51 shows a timing protocol for DrdybCase1. In this case, start by asserting CSB first to monitor a drdyb
assertion. When the drdyb signal asserts, begin writing the Instruction Bytes (INST1, UAB, INST2) to read from
or write to registers. Note that INST1 and UAB are omitted from the figure below because this transaction is only
required if a new UAB needs to be implemented.
While the CSB is asserted, DRDYB is driving the SDO/DRDYB pin unless the device is reading data, in which
case, SDO will be driving the pin. If CSB is deasserted, then the SDO/DRDYB pin is High-Z.
Figure 51. Timing Protocol for DrdybCase1
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Links: LMP90077 LMP90078 LMP90079 LMP90080