Datasheet

1/ODR
1/ODR
SDO
LSB
D6 = drdyb
Valid
ADC_DOUT
(ADC Data 1)
MSB
LSB
Valid
ADC_DOUT
(ADC Data 2)
MSB
ADC
Data 2
ADC
Data 1
DRDYB:
SDO:
1/ODR
t
DRDYB
. . .
LMP90077, LMP90078, LMP90079, LMP90080
SNAS521F –JULY 2011–REVISED MARCH 2013 www.ti.com
CSB - Chip Select Bar
An SPI transaction begins when the master asserts (active low) CSB and ends when the master deasserts
(active high) CSB. Each transaction might be separated by a subsequent one with a CSB deassertion, but this is
optional. Once CSB is asserted, it must not pulse (deassert and assert again) during a (desired) transaction.
CSB can be grounded in systems where LMP900xx is the only SPI slave. This frees the software from handling
the CSB. Care has to be taken to avoid any false edge on SCLK, and while operating in this mode, the streaming
transaction should not be used because exiting from this mode can only be done through a CSB deassertion.
SPI Reset
SPI Reset resets the SPI-Protocol State Machine by monitoring the SDI for at least 73 consecutive 1's at each
SCLK rising edge. After an SPI Reset, SDI is monitored for a possible Write Instruction at each SCLK rising
edge.
SPI Reset will reset the Upper Address Register (URA) to 0, but the register contents are not reset.
By default, SPI reset is disabled, but it can be enabled by writing 0x01 to SPI Reset Register (ADDR 0x02).
DRDYB - Data Ready Bar
DRDYB is a signal generated by the LMP900xx that indicates a fresh conversion data is available in the
ADC_DOUT registers.
DRDYB is automatically asserted every (1/ODR) second as seen in Figure 48. Before the next assertion, DRDYB
will pulse for t
DRDYB
second. The value for t
DRDYB
can be found in Timing Diagrams.
Figure 48. DRDYB Behavior
If ADC_DOUT is being read while a new ADC_DOUT becomes available, then the ADC_DOUT that is being
read is still valid (Figure 49). DRDYB will still be deasserted every 1/ODR second, but a consecutive read on the
ADC_DOUT register will fetch the newly converted data available.
Figure 49. DRDYB Behavior for an Incomplete ADC_DOUT Reading
DRDYB can also be accessed via registers using the DT_AVAIL_B bit. This bit indicates when fresh conversion
data is available in the ADC_DOUT registers. If new conversion data is available, then DT_AVAIL_B = 0;
otherwise, DT_AVAIL_B = 1.
A complete reading for DT_AVAIL_B occurs when the MSB of ADC_DOUTH is read out. This bit cannot be reset
even if REG_AND_CNV_RST = 0xC3.
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