Datasheet

R/WB = Read/Write Data
0: Write Data
1: Read Data
7 [3:0] [N:0]
R/WB SZ
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
[6:5] 4
0
Lower Register
Address (LRA)
Data Byte (s)
Instruction Byte 2 (INST2)
Data Byte (s)
[7:0] [7:3] [2:0]
0x0
Upper Register
Address (URA)
Instruction Byte 1 (INST1)
Upper Address Byte (UAB)
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
RA/WAB
Transaction 2 ± Data Access
Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
LMP90077, LMP90078, LMP90079, LMP90080
www.ti.com SNAS521F –JULY 2011–REVISED MARCH 2013
Register Read/Write Protocol
Figure 47 shows the protocol how to write to or read from a register.
Transaction 1 sets up the upper register address (URA) where the user wants to start the register-write or
register-read.
Transaction 2 sets the lower register address (LRA) and includes the Data Byte(s), which contains the incoming
data from the master or outgoing data from the LMP900xx.
Examples of register-reads or register-writes can be found in Register Read/Write Examples.
Figure 47. Register Read/Write Protocol
Streaming
When writing/reading 3+ bytes, the user must operate the device in Normal Streaming mode or Controlled
Streaming mode. In the Normal Streaming mode, which is the default mode, data runs continuously starting from
ADDR until CSB deasserts. This mode is especially useful when programming all the configuration registers in a
single transaction. See Normal Streaming Example for an example of the Normal Streaming mode.
In the Controlled Streaming mode, data runs continuously starting from ADDR until the data has run through all
(STRM_RANGE + 1) registers. For example, if the starting ADDR is 0x1C, STRM_RANGE = 5, then data will be
written to or read from the following ADDRs: 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21. Once the data reaches ADDR
0x21, LMP900xx will wrap back to ADDR 0x1C and repeat this process until CSB deasserts. See Controlled
Streaming Example for an example of the Controlled Streaming mode.
If streaming reaches ADDR 0x7F, then it will wrap back to ADDR 0x00. Furthermore, reading back the Upper
Register Address after streaming will report the Upper Register Address at the start of streaming, not the Upper
Register Address at the end of streaming.
To stream, write 0x3 to INST2’s SZ bits as seen in Figure 47. To select the stream type, program the
SPI_STREAMCN: STRM_TYPE bit. The STRM_RANGE can also be programmed in the same register.
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