Datasheet

LMP90077, LMP90078, LMP90079, LMP90080
www.ti.com SNAS521F –JULY 2011–REVISED MARCH 2013
Functional Description
Throughout this datasheet, the LMP90080/LMP90079/LMP90078/LMP90077 will be referred to as the
LMP900xx.
The LMP900xx is a low-power 16-Bit ΣΔ ADC with 4 fully differential / 7 single-ended analog channels for the
LMP90080/LMP90079 and 2 full differential / 4 single-ended for the LMP90078/LMP90077. Its serial data output
is two’s complement format. The output data rate (ODR) ranges from 1.6775 SPS to 214.65 SPS.
The serial communication for LMP900xx is SPI, a synchronous serial interface that operates using 4 pins: chip
select bar (CSB), serial clock (SCLK), serial data in (SDI), and serial data out / data ready bar (SDO/DRYDYB).
True continuous built-in offset and gain background calibration is also available to improve measurement
accuracy. Unlike other ADCs, the LMP900xx’s background calibration can run without heavily impacting the input
signal. This unique technique allows for positive as well as negative gain calibration and is available at all gain
settings.
The registers can be found in Registers, and a detailed description of the LMP900xx are provided in the following
sections.
SIGNAL PATH
Reference Input (V
REF
)
The differential reference voltage V
REF
(V
REFP
– V
REFN
) sets the range for V
IN
.
The muxed V
REF
allows the user to choose between V
REF1
or V
REF2
for each channel. This selection can be
made by programming the V
REF_SEL
bit in the CHx_INPUTCN registers (CHx_INPUTCN: V
REF_SEL
). The default
mode is V
REF1
. If V
REF2
is used, then V
IN6
and V
IN7
cannot be used as inputs because they share the same pin.
Refer to V
REF
for V
REF
applications information.
Flexible Input MUX (VIN)
LMP900xx provides a flexible input MUX as shown in Figure 31. The input that is digitized is V
IN
= V
INP
– V
INN
;
where V
INP
and V
INN
can be any availablie input.
The digitized input is also known as a channel, where CH = V
IN
= V
INP
– V
INN
. Thus, there are a maximum of 4
differential channels: CH0, CH1, CH2, and CH3 for the LMP90080/LMP90079. The LMP90078/LMP90077 has 2
differential channels: CH0 and CH1 because it does not have the V
IN3
, V
IN4
, and V
IN5
pins.
LMP900xx can also be configured single-endedly, where the common ground is any one of the inputs. There are
a maximum of 7 single-ended channels: CH0, CH1, CH2, CH3, CH4, CH5, and CH6 for the
LMP90080/LMP90079 and 4: CH0, CH1, CH2, CH3 for the LMP90078/LMP90077.
The input MUX can be programmed in the CHx_INPUTCN registers. For example on the LMP90080, to program
CH0 = V
IN
= V
IN4
– V
IN1
, go to the CH0_INPUTCN register and set:
1. V
INP
= 0x4
2. V
INN
= 0x1
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