Datasheet

SCLK
SDI
DB
0.3V
IO
0.7V
IO
0.3V
IO
0.7V
IO
0.7V
IO
t
DIH
t
DISU
SCLK
0.9V
IO
0.1V
IO
t
CLKF
t
CLKR
0.1V
IO
0.9V
IO
CSB
SCLK
0.7V
IO
t
CSHmin
CSB
SCLK
0.3V
IO
0.7V
IO
t
CSSUmin
CSB
SCLK
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
n
LSB
INST2
SDI
MSB
SDO/
DRDYB
Data Byte (s)
DRDYB is driving the pin
SDO is driving the pin
LSB
1/f
SCLK
t
CL
t
CH
...
LMP90077, LMP90078, LMP90079, LMP90080
www.ti.com SNAS521F –JULY 2011–REVISED MARCH 2013
Timing Diagrams
Unless otherwise noted, specified limits apply for V
A
= V
IO
= 3.0V. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
; the
typical values apply for T
A
= +25°C.
Figure 3. Timing Diagram
Symbol Parameter Conditions Min Typical Max Units
f
SCLK
10 MHz
t
CH
SCLK High time 0.4 / f
SCLK
ns
t
CL
SCLK Low time 0.4 / f
SCLK
ns
Symbol Parameter Conditions Min Typical Max Units
t
CSSU
CSB Setup time prior to an SCLK rising edge 5 ns
t
CSH
CSB Hold time after the last rising edge of SCLK 6 ns
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