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Table Of Contents

LMP90077, LMP90078, LMP90079, LMP90080

www.ti.com

SNAS521F –JULY 2011–REVISED MARCH 2013

LMP90080/LMP90079/LMP90078/LMP90077 Sensor AFE System: Multi-Channel, Low-

Power 16-Bit Sensor AFE with True Continuous Background Calibration

Check for Samples: LMP90077, LMP90078, LMP90079, LMP90080

FEATURES

APPLICATIONS

• 16-Bit Low-Power Sigma Delta ADC

• Temperature and Pressure Transmitters

• True Continuous Background Calibration at All • Strain Gauge Interface

Gains

• Industrial Process Control

• In-Place System Calibration Using Expected

Value Programming DESCRIPTION

The LMP90080/LMP90079/LMP90078/LMP90077 are

• Low-Noise Programmable Gain (1x - 128x)

highly integrated, multi-channel, low-power 16-bit

• Continuous Background Open/Short and Out

Sensor AFEs. The devices feature a precision, 16-bit

of Range Sensor Diagnostics

Sigma Delta Analog-to-Digital Converter (ADC) with a

• 8 Output Data Rates (ODR) with Single-Cycle

low-noise programmable gain amplifier and a fully

Settling

differential high impedance analog input multiplexer.

A true continuous background calibration feature

• 2 Matched Excitation Current Sources from

allows calibration at all gains and output data rates

100 µA to 1000 µA (LMP90080/LMP90078)

without interrupting the signal path. The background

• 4-DIFF / 7-SE Inputs (LMP90080/LMP90079)

calibration feature essentially eliminates gain and

• 2-DIFF / 4-SE Inputs (LMP90078/LMP90077)

offset errors across temperature and time, providing

measurement accuracy without sacrificing speed and

• 7 General Purpose Input/Output Pins

power consumption.

• Chopper-Stabilized Buffer for Low Offset

Another feature of the LMP90080/LMP90079

• SPI 4/3-Wire with CRC Data Link Error

/LMP90078/LMP90077 is continuous background

Detection

sensor diagnostics, allowing the detection of open

• 50 Hz to 60 Hz Line Rejection at ODR ≤13.42

and short circuit conditions and out-of-range signals,

SPS

without requiring user intervention, resulting in

enhanced system reliability.

• Independent Gain and ODR Selection per

Channel

Two sets of independent external reference voltage

• Supported by WEBENCH

Sensor AFE

pins allow multiple ratiometric measurements. In

addition, two matched programmable current sources

Designer

are available in the LMP90080/LMP90078 to excite

• Automatic Channel Sequencer

external sensors such as resistive temperature

detectors and bridge sensors. Furthermore, seven

KEY SPECIFICATIONS

GPIO pins are provided for interfacing to external

• ENOB/NFR: Up to 16/16 Bits LEDs and switches to simplify control across an

isolation barrier.

• Offset Error (typ): 8.4 nV

Collectively, these features make the LMP90080

• Gain Error (typ): 7 ppm

/LMP90079/LMP90078/LMP90077 complete analog

• Total Noise: <10 µV-rms

front-ends for low-power, precision sensor

• Integral Non-Linearity (INL Max): ±1 LSB

applications such as temperature, pressure, strain

• Output Data Rates (ODR): 1.6775 - 214.65 SPS gauge, and industrial process control. The

LMP90080/LMP90079/LMP90078/LMP90077 are

• Analog Voltage, V

: +2.85 to +5.5 V

ensured over the extended temperature range of -

• Operating Temp Range: -40 to 125°C

40°C to +125°C and are available in a 28-pin

• Package: 28 Pin Exposed Pad

package with an exposed pad.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2WEBENCH is a registered trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (64 pages)

PAGE 1
LMP90077, LMP90078, LMP90079, LMP90080 www.ti.
PAGE 2
LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Typical Application VIO VREFP1 VREFN1 2 -Wire RTD 3-Wire RTD VA 4-Wire RTD Thermocouple VA IB1 LM90xxx 16-bit Sensor AFE Family of Products CSB 2 3 4 VIN7/ VREFN2 MicroController SDO/DRDYB VIN0 ... VIN2 ... VIN4 ... VIN6/VREFP2 1 + SCLK IB2 LMP90080 SDI D0 ...
PAGE 3
LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 True Continuous Background Calibration The LMP90080/LMP90079/LMP90078/LMP90077 feature a 16 bit ΣΔ core with continuous background calibration to compensate for gain and offset errors in the ADC, virtually eliminating any drift with time and temperature.
PAGE 4
LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.
PAGE 5
LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) (4) Analog Supply Voltage, VA -0.3V to 6.0V Digital I/O Supply Voltage, VIO -0.3V to 6.0V Reference Voltage, VREF -0.3V to VA+0.3V Voltage on Any Analog Input Pin to GND (5) Voltage on Any Digital Input PIN to GND -0.3V to VA+0.3V (5) -0.3V to VIO+0.3V Voltage on SDO (5) -0.3V to VIO + 0.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol n Parameter Conditions Min Typ Resolution ENOB / NFR ODR INL Effective Number of Bits and Noise Free Resolution 3V / all / ON / OFF / all. Shorted input.
PAGE 7
LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Electrical Characteristics (continued) Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol Parameter Cross-talk Min Typ 3V / 214.65 / OFF / OFF / 1 Conditions 95 136 Max Units dB 5V / 214.
PAGE 8
LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol Parameter Conditions Min Typ Max Units CINP Capacitance of the 5V / 214.65 / OFF / OFF / 1 Positive Input 4 pF CINN Capacitance of the 5V / 214.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Electrical Characteristics (continued) Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol Parameter IBMT Conditions IB1/IB2 Matching IB1/IB2 Matching Drfit IBMTC Typ Max Units 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 100 µA Min 0.34 1.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Table 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V ODR (SPS) Gain of the ADC 1 2 4 8 16 32 64 128 1.6775 3.08 1.90 1.53 1.27 0.23 0.21 0.15 0.14 3.355 4.56 2.70 2.21 1.67 0.34 0.27 0.24 0.26 6.71 6.15 4.10 3.16 2.39 0.51 0.40 0.37 0.35 13.42 8.60 5.85 4.29 3.64 0.67 0.54 0.51 0.49 26.83125 3.35 2.24 1.65 1.33 0.33 0.27 0.26 0.25 53.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Timing Diagrams Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. CSB tCH SCLK 1 2 3 1/fSCLK tCL 4 5 6 7 8 9 10 11 12 13 14 15 16 n 17 INST2 SDI MSB LSB DRDYB is driving the pin SDO is driving the pin Data Byte (s) SDO/ DRDYB MSB LSB ... Figure 3.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 Symbol www.ti.com Parameter Conditions Min Typical Max Units tCLKR SCLK Rise time 1.15 ns tCLKF SCLK Fall time tDISU SDI Setup time prior to an SCLK rising edge 5 1.15 ns ns tDIH SDI Hold time after an SCLK rising edge 6 ns 0.7VIO SCLK 0.3VIO CSB t DOH t DOD1 t DOA 0.9VIO 0.7VIO 0.7VIO 0.3VIO 0.3VIO Symbol DB0 SDO DB DB SDO 0.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Specific Definitions COMMON MODE REJECTION RATIO is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C.
PAGE 15
LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C. Noise vs. Gain without Calibration at ODR = 13.42 SPS Noise vs. Gain with Calibration at ODR = 13.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C. Offset Error vs. Temperature without Calibration at Gain = 8 Offset Error vs. Temperature with Calibration at Gain = 8 0.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C. Digital Filter Frequency Response 0 -20 -20 -40 -40 GAIN (dB) GAIN (dB) Digital Filter Frequency Response 0 -60 -80 -60 -80 1.7 SPS 3.4 SPS 6.7 SPS 13.4 SPS -100 26.83 SPS 53.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Functional Description Throughout this datasheet, the LMP90080/LMP90079/LMP90078/LMP90077 will be referred to as the LMP900xx. The LMP900xx is a low-power 16-Bit ΣΔ ADC with 4 fully differential / 7 single-ended analog channels for the LMP90080/LMP90079 and 2 full differential / 4 single-ended for the LMP90078/LMP90077. Its serial data output is two’s complement format. The output data rate (ODR) ranges from 1.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com VREFP1 VIN0 VIN1 VIN2 VIN3* VINP + + - ADC BUFF FGA VINN + - - VIN4* VIN5* VIN6/VREFP2 VIN7/VREFN2 VREFN1 * VIN3, VIN4, VIN5 are only available for LMP90080 and LMP90079 Figure 31. Simplified VIN Circuitry Selectable Gains (FGA & PGA) LMP900xx provides two types of gain amplifiers: a fixed gain amplifier (FGA) and a programmable gain amplifier (PGA).
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Note that these ODRs are meant for a single channel conversion; the ODR needs to be divided by n for n channels scanning. For example, if the ADC were running at 214.65 SPS and four channels are being scanned, then the ODR per channel would be 214.65/4 = 53.6625 SPS.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 -60 13.42 SPS -70 GAIN (dB) -80 -90 -100 -110 -120 45 47 49 51 53 55 57 59 61 63 65 1800 2000 FREQUENCY (Hz) Figure 35. Digital Filter Response at 13.42 SPS 0 26.83125 SPS 53.6625 SPS GAIN (dB) -40 -80 -120 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY (Hz) Figure 36. Digital Filter Response, 26.83125 SPS and 53.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com 0 107.325 SPS 214.65 SPS GAIN (dB) -40 -80 -120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (Hz) Figure 37. Digital Filter Response 107.325 SPS and 214.65 SPS If the internal CLK is not being used and the external CLK is not 3.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 inputs outputs Pins D0 ± D6 = Set GPIO_DIRCNx = 0 Set GPIO_DIRCNx = 1 Read the GPIO_DAT: Dx bit to determine if Dx is high or low, where 0 7 x 7 6. Write to GPIO_DAT: Dx bit to drive Dx high or low, where 0 7 x 7 6. Figure 39. GPIO Register Settings CALIBRATION As seen in Figure 40, there are two types of calibration: background calibration and system calibration.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com The benefits of using type 2 calibration is a higher throughput, lower power consumption, and slightly better noise. The exact savings would depend on the number of channels being scanned, and the ODR and gain of each channel. Using Background Calibration: There are four modes of background calibration, which can be programmed using the BGCALCN bits. They are as follows: 1. BgcalMode0: Background Calibration OFF 2.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 System Calibration The LMP900xx provides some unique features to support easy system offset and system gain calibrations. The System Calibration Offset Registers (CHx_SCAL_OFFSET) hold the System Calibration Offset Coefficients in 16-bit, two's complement binary format. The System Calibration Gain Registers (CHx_SCAL_GAIN) hold the System Calibration Gain Coefficient in 16-bit, 1.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com System Calibration Gain Coefficient Determination mode 1. Repeat the System Calibration Offset Coefficient Determination to calibrate the System offset for the channel. 2. Apply the system reference-scale condition to the channel CH0/CH1/CH2/CH3. 3. In the CHx_SCAL_GAIN register, program the expected (desired) system-calibrated output code for this condition in 16-bit unsigned format. 4.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 ScanMode1: Multiple-Channels Single Scan LMP900xx converts one or more channels starting from FIRST_CH to LAST_CH, and then enters the stand-by state. ScanMode2: Multiple-Channels Continuous Scan LMP900xx continuously converts one or more channels starting from FIRST_CH to LAST_CH, and then it repeats this process.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Burnout Current = 10 PA VIN0 VIN1 VIN2 VIN3 VINP VINN VIN4 VIN5 VIN6/VREFP2 VIN7/VREFN2 Burnout Current = 10 PA * VIN3, VIN4, VIN5 are only available for LMP90080 and LMP90079 Figure 44. Burnout Currents Burnout Current Injection: Burnout currents are injected differently depending on the channel scan mode selected.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Burnout Currents BURNOUT_EN CH0 is being sampled CH0 CH1 CH2 CH3 BURNOUT_EN CH1 is being sampled CH0 CH1 CH2 CH3 BURNOUT_EN CH2 is being sampled CH0 CH1 CH2 CH3 BURNOUT_EN CH3 is being sampled CH0 CH1 CH2 CH3 Figure 45.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com SHORT_THLD_FLAG: The short circuit threshold flag is used to report a short-circuit condition. It is set when the output voltage (VOUT) is within the absolute Vthreshold. Vthreshold can be programmed using the 8-bit SENDIAG_THLDH register. For example, assume VREF = 5V, gain = 1, SENDIAG_THLD = 0xDA (218d).
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Register Read/Write Protocol Figure 47 shows the protocol how to write to or read from a register. Transaction 1 sets up the upper register address (URA) where the user wants to start the register-write or register-read. Transaction 2 sets the lower register address (LRA) and includes the Data Byte(s), which contains the incoming data from the master or outgoing data from the LMP900xx.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com CSB - Chip Select Bar An SPI transaction begins when the master asserts (active low) CSB and ends when the master deasserts (active high) CSB. Each transaction might be separated by a subsequent one with a CSB deassertion, but this is optional. Once CSB is asserted, it must not pulse (deassert and assert again) during a (desired) transaction. CSB can be grounded in systems where LMP900xx is the only SPI slave.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 DrdybCase1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00 uC LMP900xx SCLK SCLK CSB CSB SDI MOSI SDO/ DRDYB MISO INT Figure 50. DrdybCase1 Connection Diagram As shown in Figure 50, the drdyb signal and SDO can be multiplexed on the same pin as their functions are mostly complementary. In fact, this is the default mode for the SDO/DRDYB pin. Figure 51 shows a timing protocol for DrdybCase1.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com DrdybCase2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03 SDO/DRDYB can be made independent of CSB by setting SDO_DRDYB_DRIVER = 0x03 in the SPI Handshake Control register. In this case, DRDYB will drive the pin unless the device is reading data, independent of the state of CSB. SDO will drive the pin when CSB is asserted and the device is reading data.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 CSB SCLK 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 n INST2 SDI MSB LSB Drdyb = D6 ... Data Byte (s) High-Z SDO MSB LSB Figure 54. Timing Protocol for DrdybCase3 Data Only Read Transaction In a data only read transaction, one can directly access the data byte(s) as soon as the CSB is asserted without having to send any instruction byte.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Cyclic Redundancy Check (CRC) CRC can be used to ensure integrity of data read from LMP900xx. To enable CRC, set EN_CRC high. Once CRC is enabled, the CRC value is calculated and stored in SPI_CRC_DAT so that the master device can periodically read for data comparison. The CRC is automatically reset when CSB or DRDYB is deasserted. The CRC polynomial is x8 + x5 + x4 + 1.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 POWER MANAGEMENT The device can be placed in Active, Power-Down, or Stand-By state. In Power-Down, the ADC is not converting data, contents of the registers are unaffected, and there is a drastic power reduction. In Stand-By, the ADC is not converting data, but the power is only slightly reduced so that the device can quickly transition into the active state if desired.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION QUICK START This section shows step-by-step instructions to configure the LMP900xx to perform a simple DC reading from CH0. 1. Apply VA = VIO = VREFP1 = 5V, and ground VREFN1 2. Apply VINP = ¾VREF and VINN = ¼VREF for CH0. Thus, set CH0 = VIN = VINP - VINN = ½VREF (CH0_INPUTCN register) 3. Set gain = 1 (CH0_CONFIG: GAIN_SEL = 0x0) 4.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 ADC_DOUT 0x7FFF or 32767d -1 LSB | | (-VREF + 1LSB) 1d | | +1LSB 0xFFFF or -65535d VIN (VREF - 1LSB) | | 0x8000 or -32768d Figure 58. ADC_DOUT vs. VIN of a 16-Bit Resolution (VREF = 5.5V, Gain = 1).
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com The next example shows how to write one data byte to ADDR 0x12. Since the URA for this example is the same as the last example, transaction 1 can be omitted. Transaction 2 ± Data Access Instruction Byte 2 (INST2) Data Byte (s) 7 [6:5] 4 [3:0] [7:0] 0 0x00 0 0x2 One Data Byte will be written to ADDR 0x12. After this process, deassert CSB.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 STREAMING EXAMPLES Normal Streaming Example This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode. Because the default STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can be omitted. Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 EXAMPLE APPLICATIONS 3–Wire RTD + 1 PF 3V 3V VA VIO + 0.1 PF 0.1 PF 1 PF SCLK IB1 CSB IB1 = 1 mA SDO SDI drdyb = D6 VIN0 LMP90080 RLINE1 RTD PT-100 RCOMP = 0: D5 VIN1 RLINE2 Microcontroller IB2 = 1 mA IB2 12 pF VIN6/VREFP2 RLINE3 3.57 MHz XOUT RREF VIN7/VREFN2 XIN/CLK 12 pF Figure 65.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com 3V 3V + + 0.1 PF 2.2 PF VA 0.1 PF VIO 1 PF SCLK IB1 IB1 = 1 mA CSB SDO/DRDYB RLINE1 SDI VIN0 Microcontroller RTD PT-100 LMP90080 D2 VIN1 RLINE2 VIN6/VREFP2 RLINE3 RREF OSC XIN/CLK VIN7/VREFN2 51: Figure 66. Topology #2: 3-wire RTD Using 1 Current Source Figure 66 shows the second topology for a 3-wire RTD application. Topology #2 shows the same connection as topology #1, but without IB2.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Thermocouple and IC Analog Temperature 5V 2.7V VA VIO + + 0.1 PF 1 PF Thermocouple Tcold SCLK VIN4 Thot 10 nF VREFP1 CSB + TC [ VIN4 ± VIN3] - 2.2 PF 1 PF 0.1 PF SDO 2k SDI VIN3 2k D6 = DRDYB 10 nF LMP90080 Microcontroller 5V LM94022 IC Temp Sensor + 1 PF Tcold VIN5 + LM [ VIN5] - 0.1 PF VIN7 XOUT 5V VREFP1 LM4140-4.1 + 1 PF 0.1 PF 0.1 PF XIN/CLK GND Figure 67.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Registers 1. If written to, RESERVED bits must be written to only 0 unless otherwise indicated. 2. Read back value of RESERVED bits and registers is unspecified and should be discarded. 3. Recommended values must be programmed and forbidden values must not be programmed where they are indicated in order to avoid unexpected results. 4.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Table 7.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Table 10. PWRCN Power Mode Control and Status (Address 0x08) Bit Bit Symbol Bit Description [7:2] Reserved Power Control Write Only – power down mode control 0x0: Active Mode 0x1: Power-down Mode 0x3: Stand-by Mode [1:0] PWRCN Read Only – the present mode is: 0x0 (default): Active Mode 0x1: Power-down Mode 0x3: Stand-by Mode ADC REGISTERS Table 11.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Table 13. ADC_DONE ADC Data Available (Address 0x18) Bit Bit Symbol [7:0] DT_AVAIL_B Bit Description Data Available – indicates if new conversion data is available 0x00 − 0xFE: Available 0xFF: Not available Table 14.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Table 16. CH_SCAN(1) (continued) Channel Scan Mode (Address 0x1F) Bit Bit Symbol Bit Description Starting channel for conversion 0x0 (default): CH0 0x1: CH1 0x2: CH2 0x3: CH3 0x4: CH4 0x5: CH5 0x6: CH6 (3) FIRST_CH (CH4 to CH6 for [2:0] LMP90080 and LMP90079 only) (3) FIRST_CH cannot be greater than LAST_CH. For example, if FIRST_CH = CH1, then LAST_CH cannot be CH0. If 0x7 is written it is ignored. Table 17.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Table 18. Default VINx for CH0-CH6 VINP VINN CH0 VIN0 VIN1 CH1 VIN2 VIN3 (LMP90080/LMP90079 only) CH2 VIN4 (LMP90080/LMP90079 only) VIN5 (LMP90080/LMP90079 only) CH3 VIN6 VIN7 CH4 (LMP90080/LMP90079 only) VIN0 VIN1 CH5 (LMP90080/LMP90079 only) VIN2 VIN3 CH6 (LMP90080/LMP90079 only) VIN4 VIN5 Table 19.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Table 21.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 SENSOR DIAGNOSTIC REGISTERS Table 26. SENDIAG_THLD Sensor Diagnostic Threshold (Address 0x14) Address 0x14 Name Register Description SENDIAG_THLD Sensor Diagnostic threshold Table 27.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com Table 30. DATA_ONLY_1 Data Only Read Control 1 (Address 0x09) Bit Bit Symbol Bit Description 7 Reserved - [6:0] DATA_ONLY_ADR Start address for the Data Only Read Transaction Default: 0x1A Please refer to the description of DT_ONLY_SZ in Table 31 register. Table 31.
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LMP90077, LMP90078, LMP90079, LMP90080 www.ti.com SNAS521F – JULY 2011 – REVISED MARCH 2013 Table 34. SPI_CRC_DAT CRC Data (Address 0x1D) Bit Bit Symbol [7:0] CRC_DAT Bit Description CRC Data When written, this register reset CRC: Any Value: Reset CRC When read, this register indicates the CRC data. GPIO REGISTERS Table 35.
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LMP90077, LMP90078, LMP90079, LMP90080 SNAS521F – JULY 2011 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 58 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMP90077MHE/NOPB HTSSOP PWP 28 250 178.0 16.4 LMP90077MHX/NOPB HTSSOP PWP 28 2500 330.0 LMP90078MHE/NOPB HTSSOP PWP 28 250 178.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP90077MHE/NOPB HTSSOP PWP LMP90077MHX/NOPB HTSSOP PWP 28 250 213.0 191.0 55.0 28 2500 367.0 367.0 38.0 LMP90078MHE/NOPB HTSSOP PWP LMP90078MHX/NOPB HTSSOP PWP 28 250 213.0 191.0 55.0 28 2500 367.0 367.0 LMP90079MHE/NOPB HTSSOP 38.0 PWP 28 250 213.0 191.0 55.
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MECHANICAL DATA PWP0028A MXA28A (Rev D) www.ti.
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