Datasheet
TIME (ns)
V
OUT
(V)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0 50 100 150 200 250 300
20 pF
10 pF
V
S
= 3.3V
Output Buffer
V
S
0V
LMP8602, LMP8602Q, LMP8603, LMP8603Q
SNOSB36D –JULY 2009–REVISED MARCH 2013
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LAYOUT CONSIDERATIONS
The two input signals of the LMP8602/LMP8602Q/LMP8603/LMP8603Q are differential signals and should be
handled as a differential pair. For optimum performance these signals should be closely together and of equal
length. Keep all impedances in both traces equal and do not allow any other signal or ground in between the
traces of this signals.
The connection between the preamplifier and the output buffer amplifier is a high impedance signal due to the
100 kΩ series resistor at the output of the preamplifier. Keep the traces at this point as short as possible and
away from interfering signals.
The LMP8602/LMP8602Q/LMP8603/LMP8603Q is available in a 8–Pin SOIC package and in a 8–Pin VSSOP
package. For the VSSOP package, the bare board spacing at the solder pads of the package will be too small for
reliable use at higher voltages (V
CM
> 25V) In this situation it is strongly advised to add a conformal coating on
the PCB assembled with the LMP8602/LMP8602Q/LMP8603/LMP8603Q in VSSOP package.
DRIVING SWITCHED CAPACITIVE LOADS
Some ADCs load their signal source with a sample and hold capacitor. The capacitor may be discharged prior to
being connected to the signal source. If the LMP8602/LMP8602Q/LMP8603/ LMP8603Q is driving such ADCs
the sudden current that should be delivered when the sampling occurs may disturb the output signal. This effect
was simulated with the circuit shown in Figure 47 where the output is connected to a capacitor that is driven by a
rail to rail square wave.
Figure 47. Driving Switched Capacitive Load
This circuit simulates the switched connection of a discharged capacitor to the LMP8602/LMP8602Q/LMP8603/
LMP8603Q output. The resulting V
OUT
disturbance signals are shown in Figure 48 and Figure 49.
Figure 48. Capacitive Load Response at 3.3V
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