Datasheet

LMP8350

www.ti.com

SNOSB80B –FEBRUARY 2011–REVISED MARCH 2013

ESD PROTECTION

The LMP8350 is protected against electrostatic discharge (ESD) on all pins. The LMP8350 will survive 2000V

Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no effect on

circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMP8350 is

driven by a large signal while the device is powered down the ESD diodes will conduct . The current that flows

through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is

possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to

conserve power and still prevent unexpected operation.

BOARD LAYOUT

While the main signal path frequencies may be fairly low, the ultra-low distortion and settling time specifications

rely on wide internal bandwidths. Precautions usually taken for high speed amplifiers should be followed to

maintain the best settling times and lowest distortion specifications. In order to get maximum benefit from the

differential circuit architecture, board layout and component selection is very critical. The circuit board should

have low a inductance ground plane and well bypassed broad supply lines. External components should be

leadless surface mount types. The feedback network and output matching resistors should be composed of short

traces and precision resistors (0.1%). The output matching resistors should be placed within 3-4 mm of the

amplifier as should the supply bypass capacitors.

The LMP8350 is sensitive to parasitic capacitances on the outputs. Ground and power plane metal should be

removed from beneath the amplifier and from beneath R

and R

With any differential signal path symmetry is very important. Even small amounts of asymmetry will contribute to

distortion and balance errors. Special attention should be paid to where the bypass capacitors are grounded, as

this also affects settling and distortion performance.

The LMH730154 evaluation board is an example of good layout techniques. Evaluation boards are available for

purchase through the product folder on TI’s web site.

EVALUATION BOARD

Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input

and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and

possible circuit oscillations (see Application Note OA-15 for more information). Texas Instruments suggests the

following evaluation boards as a guide for high frequency layout and as an aid in device testing and

characterization:

Device Package Evaluation Board Part Number

LMP8350MA SOIC LMH730154

Product Folder Links: LMP8350