Datasheet

V
OCM
V
+
10 PF
0.1 PF
+
-
0.01 PF
0.1 PF
V
OCM
0.1 PF
V
+
V
-
0.01 PF
0.01 PF
10 PF
10 PF
0.1 PF
+
-
LMP8350
www.ti.com SNOSB80B –FEBRUARY 2011–REVISED MARCH 2013
Figure 35. Split Supply Bypassing Capacitors
The 0.01 µF and 0.1 µF capacitors should be leadless surface mount (SMT) ceramic capacitors and should be
no more than 3 mm from the supply pins. The SMT capacitors should be connected directly to a ground plane.
Thin traces or small vias will reduce the effectiveness of bypass capacitors.
Figure 36. Single Supply Bypassing Capacitors
Also shown in both figures is a capacitor from the V
OCM
pin to ground. The V
OCM
pin sets the output common
mode voltage. Any noise on this input is transferred directly to the output. The V
OCM
pin should be bypassed
even if the pin in not used. There is an internal resistive divider on chip to set the output common mode voltage
to the mid point of the supply pins. The impedance looking into this pin is approximately 30 kΩ. If a different
output common mode voltage is desired drive this pin with a clean, accurate voltage reference.
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog to digital converters (ADC) present challenging load conditions. They typically have high impedance
inputs with large and often variable capacitive components. As well, there are usually current spikes associated
with switched capacitor or sample and hold circuits. Figure 37 shows a typical circuit for driving an ADC. The two
resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In addition, the
resistors form part of a low pass filter which helps to provide anti alias and noise reduction functions. The C
S
capacitor helps to smooth the current spikes associated with the internal switching circuits of the ADC and also
are a key component in the low pass filtering of the ADC input. The capacitor should be a low distortion
capacitor, such as an NPO, to avoid causing significant distortion terms. In the circuit of Figure 37, the cutoff
frequency of the filter is 1/ (2*π*(R
ISO1
+R
ISO2
) *(C
S
+ C
CONVERTER
)), which should be slightly less than the
sampling frequency. Note that the ADC input capacitance must be factored into the frequency response of the
input filter. Also as shown in Figure 37, the input capacitance to many ADCs is variable based on the clock cycle.
For lower speed, precision ADC's, the external cap is generally sized to ten times the internal sampling capacitor
value. See the data sheet for your particular ADC for details.
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